# Synopsys Constraint Checker, version maplat, Build 1796R, built Aug 4 2017 # Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. # Written on Thu Aug 8 18:39:12 2019 ##### DESIGN INFO ####################################################### Top View: "FleaFPGA_Uno_E1" Constraint File(s): (none) ##### SUMMARY ############################################################ Found 0 issues in 0 out of 0 constraints ##### DETAILS ############################################################ Clock Relationships ******************* Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 | No paths | No paths | No paths System dm7427|y1_inferred_clock | 1000.000 | No paths | No paths | No paths System dm7400_1|y1_inferred_clock | 1000.000 | No paths | No paths | No paths FleaFPGA_Uno_E1|sys_clock FleaFPGA_Uno_E1|sys_clock | 1000.000 | No paths | No paths | No paths FleaFPGA_Uno_E1|sys_clock master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths FleaFPGA_Uno_E1|sys_clock dm7427|y1_inferred_clock | Diff grp | No paths | No paths | No paths FleaFPGA_Uno_E1|sys_clock dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths FleaFPGA_Uno_E1|sys_clock dm74161_4|count_derived_clock[3] | Diff grp | No paths | No paths | No paths master_clk|CLKOS_inferred_clock master_clk|CLKOS_inferred_clock | 1000.000 | No paths | No paths | No paths master_clk|CLKOS_inferred_clock dm7427|y1_inferred_clock | Diff grp | No paths | No paths | No paths master_clk|CLKOS_inferred_clock dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths master_clk|CLKOS_inferred_clock dm74175|q0_i_inferred_clock | Diff grp | No paths | No paths | No paths master_clk|CLKOS_inferred_clock dm74161_4|count_derived_clock[3] | Diff grp | No paths | No paths | No paths dm7400_1|y3_inferred_clock dm7400_1|y3_inferred_clock | No paths | 1000.000 | No paths | No paths dm7400_1|y3_inferred_clock dm7400_1|y1_inferred_clock | No paths | No paths | No paths | Diff grp dm7427|y1_inferred_clock System | 1000.000 | No paths | No paths | No paths dm7427|y1_inferred_clock FleaFPGA_Uno_E1|sys_clock | Diff grp | No paths | No paths | No paths dm7427|y1_inferred_clock master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths dm7427|y1_inferred_clock dm7427|y1_inferred_clock | 1000.000 | No paths | No paths | No paths dm7427|y1_inferred_clock dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths dm7427|y1_inferred_clock dm74161_4|count_derived_clock[3] | Diff grp | No paths | No paths | No paths dm7400_1|y1_inferred_clock System | 1000.000 | No paths | No paths | No paths dm7400_1|y1_inferred_clock master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths dm7400_1|y1_inferred_clock dm7400_1|y1_inferred_clock | 1000.000 | No paths | No paths | No paths dm74175|q0_i_inferred_clock dm74175|q0_i_inferred_clock | 1000.000 | No paths | No paths | No paths dm74161_4|count_derived_clock[3] master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths dm74161_4|count_derived_clock[3] dm7427|y1_inferred_clock | Diff grp | No paths | No paths | No paths dm74161_4|count_derived_clock[3] dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths dm74161_4|count_derived_clock[3] dm74175|q0_i_inferred_clock | 1000.000 | No paths | No paths | No paths dm74161_4|count_derived_clock[3] dm74161_4|count_derived_clock[3] | 1000.000 | No paths | No paths | No paths ===================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Unconstrained Start/End Points ****************************** p:Audio_l p:Audio_r p:NTSC_DAC[0] p:NTSC_DAC[1] p:NTSC_DAC[2] p:NTSC_DAC[3] p:SRAM_n_cs p:User_LED1 p:User_LED2 p:User_PB1 p:slave_rx_i p:spi1_cs p:sync Inapplicable constraints ************************ (none) Applicable constraints with issues ********************************** (none) Constraints with matching wildcard expressions ********************************************** (none) Library Report ************** # End of Constraint Checker Report