[ActiveSupport MAP]
Device = LCMXO2-7000HC;
Package = TQFP144;
Performance = 4;
LUTS_avail = 6864;
LUTS_used = 300;
FF_avail = 6979;
FF_used = 175;
INPUT_LVCMOS33 = 3;
OUTPUT_LVCMOS25 = 3;
OUTPUT_LVCMOS33 = 9;
IO_avail = 115;
IO_used = 15;
EBR_avail = 26;
EBR_used = 9;
; Begin EBR Section
Instance_Name = apple_module/C11b/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
Instance_Name = apple_module/C3/LineBuffer/sram_1_0_0_0;
Type = DP8KC;
Width_A = 6;
Depth_A = 64;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_INIT_FILE = lut_2519.mem;
MEM_LPC_FILE = ShiftReg40.lpc;
Instance_Name = apple_module/D14a/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
Instance_Name = apple_module/D14b/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
Instance_Name = apple_module/D2/sig2513_0_0_0;
Type = DP8KC;
Width_A = 5;
Depth_A = 512;
REGMODE_A = OUTREG;
REGMODE_B = OUTREG;
RESETMODE = SYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = NORMAL;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_INIT_FILE = lut_2513.mem;
MEM_LPC_FILE = sig2513.lpc;
Instance_Name = apple_module/D4a/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
Instance_Name = apple_module/D4b/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
Instance_Name = apple_module/D5a/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
Instance_Name = apple_module/D5b/sram_1_0_0_0;
Type = DP8KC;
Width_A = 1;
Depth_A = 1024;
REGMODE_A = NOREG;
REGMODE_B = NOREG;
RESETMODE = ASYNC;
ASYNC_RESET_RELEASE = SYNC;
WRITEMODE_A = READBEFOREWRITE;
WRITEMODE_B = NORMAL;
GSR = DISABLED;
MEM_LPC_FILE = sig2504.lpc;
; End EBR Section
; Begin PLL Section
Instance_Name = clock_module/PLLInst_0;
Type = EHXPLLJ;
CLKOP_Post_Divider_A_Input = DIVA;
CLKOS_Post_Divider_B_Input = DIVB;
CLKOS2_Post_Divider_C_Input = DIVC;
CLKOS3_Post_Divider_D_Input = DIVD;
Pre_Divider_A_Input = VCO_PHASE;
Pre_Divider_B_Input = VCO_PHASE;
Pre_Divider_C_Input = VCO_PHASE;
Pre_Divider_D_Input = VCO_PHASE;
VCO_Bypass_A_Input = VCO_PHASE;
VCO_Bypass_B_Input = VCO_PHASE;
VCO_Bypass_C_Input = VCO_PHASE;
VCO_Bypass_D_Input = VCO_PHASE;
FB_MODE = INT_OP;
CLKI_Divider = 1;
CLKFB_Divider = 1;
CLKOP_Divider = 20;
CLKOS_Divider = 35;
CLKOS2_Divider = 1;
CLKOS3_Divider = 1;
Fractional_N_Divider = 0;
CLKOP_Desired_Phase_Shift(degree) = 0;
CLKOP_Trim_Option_Rising/Falling = RISING;
CLKOP_Trim_Option_Delay = 0;
CLKOS_Desired_Phase_Shift(degree) = 0;
CLKOS_Trim_Option_Rising/Falling = RISING;
CLKOS_Trim_Option_Delay = 0;
CLKOS2_Desired_Phase_Shift(degree) = 0;
CLKOS3_Desired_Phase_Shift(degree) = 0;
; End PLL Section