#
# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
#

# Period Constraints 
#FREQUENCY PORT "sys_clock" 159.6 MHz;
#FREQUENCY NET "apple_module/D10/vbl_i" 314.4 MHz;
#FREQUENCY NET "apple_module/D10/y3" 314.4 MHz;
#FREQUENCY NET "apple_module/D10/vbl_i" 314.4 MHz;
#FREQUENCY NET "apple_module/D10/y3" 314.4 MHz;
#FREQUENCY NET "apple_module/C5/mem0" 292.6 MHz;
#FREQUENCY NET "apple_module/C5/y1" 292.6 MHz;
#FREQUENCY NET "apple_module/C5/mem0" 292.6 MHz;
#FREQUENCY NET "apple_module/C5/y1" 292.6 MHz;
#FREQUENCY NET "apple_module/D10/line_clock" 164.6 MHz;
#FREQUENCY NET "apple_module/D10/y1" 164.6 MHz;
#FREQUENCY NET "apple_module/D10/line_clock" 164.6 MHz;
#FREQUENCY NET "apple_module/D10/y1" 164.6 MHz;


# Output Constraints 

# Input Constraints 

# Point-to-point Delay Constraints 



# Block Path Constraints 
#BLOCK PATH FROM CLKNET "apple_module/D10/line_clock" TO CLKNET "apple_module/C5/mem0";
#BLOCK PATH FROM CLKNET "apple_module/D10/line_clock" TO CLKNET "apple_module/D10/vbl_i";
#BLOCK PATH FROM CLKNET "apple_module/D10/line_clock" TO CLKNET "sys_clock_c";
#BLOCK PATH FROM CLKNET "apple_module/C5/mem0" TO CLKNET "apple_module/D10/line_clock";
#BLOCK PATH FROM CLKNET "apple_module/C5/mem0" TO CLKNET "apple_module/D10/vbl_i";
#BLOCK PATH FROM CLKNET "apple_module/C5/mem0" TO CLKNET "sys_clock_c";
#BLOCK PATH FROM CLKNET "apple_module/D10/vbl_i" TO CLKNET "apple_module/D10/line_clock";
#BLOCK PATH FROM CLKNET "apple_module/D10/vbl_i" TO CLKNET "apple_module/C5/mem0";
#BLOCK PATH FROM CLKNET "apple_module/D10/vbl_i" TO CLKNET "sys_clock_c";
#BLOCK PATH FROM CLKNET "sys_clock_c" TO CLKNET "apple_module/D10/line_clock";
#BLOCK PATH FROM CLKNET "sys_clock_c" TO CLKNET "apple_module/C5/mem0";
#BLOCK PATH FROM CLKNET "sys_clock_c" TO CLKNET "apple_module/D10/vbl_i";

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.