[Device]
Family=machxo2
PartType=LCMXO2-7000HC
PartName=LCMXO2-7000HC-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=5.8
ModuleName=master_clk
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=08/05/2019
Time=08:34:49

[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
mode=Frequency
CLKI=25
CLKI_DIV=1
BW=2.292
VCO=500.000
fb_mode=INT_OP
CLKFB_DIV=1
FRACN_ENABLE=0
FRACN_DIV=0
DynamicPhase=STATIC
ClkEnable=0
Standby=0
Enable_sel=0
PLLRst=0
PLLMRst=0
ClkOS2Rst=0
ClkOS3Rst=0
LockSig=0
LockStk=0
WBProt=0
OPBypass=0
OPUseDiv=0
CLKOP_DIV=20
FREQ_PIN_CLKOP=25
OP_Tol=0.0
CLKOP_AFREQ=25.000000
CLKOP_PHASEADJ=0
CLKOP_TRIM_POL=Rising
CLKOP_TRIM_DELAY=0
EnCLKOS=1
OSBypass=0
OSUseDiv=0
CLKOS_DIV=35
FREQ_PIN_CLKOS=14.31818
OS_Tol=0.5
CLKOS_AFREQ=14.285714
CLKOS_PHASEADJ=0
CLKOS_TRIM_POL=Rising
CLKOS_TRIM_DELAY=0
EnCLKOS2=0
OS2Bypass=0
OS2UseDiv=0
CLKOS2_DIV=1
FREQ_PIN_CLKOS2=100
OS2_Tol=0.0
CLKOS2_AFREQ=
CLKOS2_PHASEADJ=0
EnCLKOS3=0
OS3Bypass=0
OS3UseDiv=0
CLKOS3_DIV=1
FREQ_PIN_CLKOS3=14.31818
OS3_Tol=5.0
CLKOS3_AFREQ=14.705882
CLKOS3_PHASEADJ=0

[Command]
cmd_line= -w -n master_clk -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 25 -fclkop_tol 0.0 -fclkos 14.31818 -fclkos_tol 0.5 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 5