-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
-- Module  Version: 5.7
-- Mon Aug 05 08:34:49 2019

-- parameterized module component declaration
component master_clk
    port (CLKI: in  std_logic; CLKOP: out  std_logic; 
        CLKOS: out  std_logic);
end component;

-- parameterized module component instance
__ : master_clk
    port map (CLKI=>__, CLKOP=>__, CLKOS=>__);