# messages

id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: FX474
kind: warning
message:
User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 


id: BN362
link: "c:\dev\apple1display\uart_rx.vhd":62:4:62:5
kind: note
message:
Removing sequential instance r_RX_Byte[7] (in view: work.UART_RX(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.


id: MT529
link: "c:\dev\apple1display\uart_rx.vhd":37:36:37:38
kind: warning
message:
Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: warning
message:
Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: warning
message:
Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\sig2504.vhd":187:4:187:15
kind: warning
message:
Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.D5a.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\shiftreg40.vhd":186:4:186:15
kind: warning
message:
Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: warning
message:
Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


