#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
#install: C:\lscc\diamond\3.10_x64\synpbase
#OS: Windows 8 6.2
#Hostname: MARKF-PRO

# Thu Aug  8 18:40:09 2019

#Implementation: impl1

Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N:CD720 : std.vhd(123) | Setting time resolution to ps
@N: : FleaFPGA_Uno_Top.vhd(17) | Top entity is set to FleaFPGA_Uno_E1.
Options changed - recompiling
@W:CD433 : 2504.vhd(1) | No design units in file
VHDL syntax check successful!
Options changed - recompiling
@N:CD630 : FleaFPGA_Uno_Top.vhd(17) | Synthesizing work.fleafpga_uno_e1.arch.
@W:CD326 : FleaFPGA_Uno_Top.vhd(122) | Port clkop of entity work.master_clk is unconnected. If a port needs to remain unconnected, use the keyword open.
@N:CD630 : UART_RX.vhd(18) | Synthesizing work.uart_rx.rtl.
@N:CD231 : UART_RX.vhd(33) | Using onehot encoding for type t_sm_main. For example, enumeration s_idle is mapped to "10000".
@N:CD604 : UART_RX.vhd(132) | OTHERS clause is not synthesized.
Post processing for work.uart_rx.rtl
@N:CD630 : Apple1Display.vhd(7) | Synthesizing work.apple1display.behavior.
@W:CD326 : Apple1Display.vhd(191) | Port carry of entity work.dm74161 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(226) | Port y2 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(226) | Port y1 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(233) | Port y5 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(233) | Port y3 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(233) | Port y2 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(241) | Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(321) | Port q0_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(321) | Port q1_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(321) | Port q2_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(321) | Port q3_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(321) | Port q4_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(321) | Port q5_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(354) | Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(367) | Port y4 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(367) | Port y1 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(374) | Port y3 of entity work.dm7432 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(381) | Port y3 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(381) | Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(386) | Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(386) | Port y2 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD326 : Apple1Display.vhd(386) | Port y1 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
@W:CD638 : Apple1Display.vhd(47) | Signal buffer_char_in_0 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(47) | Signal buffer_char_in_1 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(47) | Signal buffer_char_in_2 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(47) | Signal buffer_char_in_3 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(47) | Signal buffer_char_in_4 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(47) | Signal buffer_char_in_5 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(65) | Signal unconnected_1 is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Apple1Display.vhd(80) | Signal cross_talk is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : dm7400.vhd(6) | Synthesizing work.dm7400.behavior.
Post processing for work.dm7400.behavior
@N:CD630 : dm7410.vhd(6) | Synthesizing work.dm7410.behavior.
Post processing for work.dm7410.behavior
@N:CD630 : dm7432.vhd(6) | Synthesizing work.dm7432.behavior.
Post processing for work.dm7432.behavior
@N:CD630 : dm7408.vhd(6) | Synthesizing work.dm7408.behavior.
Post processing for work.dm7408.behavior
@N:CD630 : dm7450.vhd(6) | Synthesizing work.dm7450.behavior.
Post processing for work.dm7450.behavior
@N:CD630 : dm7427.vhd(6) | Synthesizing work.dm7427.behavior.
Post processing for work.dm7427.behavior
@N:CD630 : ne555.vhd(7) | Synthesizing work.ne555.behavior.
Post processing for work.ne555.behavior
@N:CD630 : dm74174.vhd(8) | Synthesizing work.dm74174.behavior.
Post processing for work.dm74174.behavior
@N:CD630 : dm74157.vhd(6) | Synthesizing work.dm74157.behavior.
Post processing for work.dm74157.behavior
@N:CD630 : sig2504.vhd(14) | Synthesizing work.sig2504.structure.
@N:CD630 : machxo2.vhd(1407) | Synthesizing work.rom16x1a.syn_black_box.
Post processing for work.rom16x1a.syn_black_box
@N:CD630 : machxo2.vhd(1699) | Synthesizing work.dp8kc.syn_black_box.
Post processing for work.dp8kc.syn_black_box
@N:CD630 : machxo2.vhd(246) | Synthesizing work.fd1p3ix.syn_black_box.
Post processing for work.fd1p3ix.syn_black_box
@N:CD630 : machxo2.vhd(167) | Synthesizing work.cu2.syn_black_box.
Post processing for work.cu2.syn_black_box
@N:CD630 : machxo2.vhd(177) | Synthesizing work.fadd2b.syn_black_box.
Post processing for work.fadd2b.syn_black_box
@N:CD630 : machxo2.vhd(1483) | Synthesizing work.vhi.syn_black_box.
Post processing for work.vhi.syn_black_box
@N:CD630 : machxo2.vhd(1490) | Synthesizing work.vlo.syn_black_box.
Post processing for work.vlo.syn_black_box
@N:CD630 : machxo2.vhd(681) | Synthesizing work.inv.syn_black_box.
Post processing for work.inv.syn_black_box
@N:CD630 : machxo2.vhd(1276) | Synthesizing work.or2.syn_black_box.
Post processing for work.or2.syn_black_box
Post processing for work.sig2504.structure
@N:CD630 : 2519.vhd(8) | Synthesizing work.ttl2519.behavior.
@N:CD630 : ShiftReg40.vhd(14) | Synthesizing work.shiftreg40.structure.
Post processing for work.shiftreg40.structure
Post processing for work.ttl2519.behavior
@N:CD630 : dm7404.vhd(6) | Synthesizing work.dm7404.behavior.
Post processing for work.dm7404.behavior
@N:CD630 : dm7402.vhd(6) | Synthesizing work.dm7402.behavior.
Post processing for work.dm7402.behavior
@N:CD630 : dm74166.vhd(6) | Synthesizing work.dm74166.behavior.
Post processing for work.dm74166.behavior
@N:CD630 : sig2513.vhd(14) | Synthesizing work.sig2513.structure.
Post processing for work.sig2513.structure
@N:CD630 : dm74161.vhd(6) | Synthesizing work.dm74161.behavior.
Post processing for work.dm74161.behavior
@N:CD630 : dm74160.vhd(6) | Synthesizing work.dm74160.behavior.
Post processing for work.dm74160.behavior
@N:CD630 : dm74175.vhd(8) | Synthesizing work.dm74175.behavior.
Post processing for work.dm74175.behavior
Post processing for work.apple1display.behavior
@W:CL240 : Apple1Display.vhd(47) | Signal buffer_char_in_5 is floating; a simulation mismatch is possible.
@W:CL240 : Apple1Display.vhd(47) | Signal buffer_char_in_4 is floating; a simulation mismatch is possible.
@W:CL240 : Apple1Display.vhd(47) | Signal buffer_char_in_3 is floating; a simulation mismatch is possible.
@W:CL240 : Apple1Display.vhd(47) | Signal buffer_char_in_2 is floating; a simulation mismatch is possible.
@W:CL240 : Apple1Display.vhd(47) | Signal buffer_char_in_1 is floating; a simulation mismatch is possible.
@W:CL240 : Apple1Display.vhd(47) | Signal buffer_char_in_0 is floating; a simulation mismatch is possible.
@W:CL167 : Apple1Display.vhd(272) | Input din of instance D14b is floating
@W:CL167 : Apple1Display.vhd(271) | Input din of instance D14a is floating
@W:CL167 : Apple1Display.vhd(270) | Input din of instance D4b is floating
@W:CL167 : Apple1Display.vhd(269) | Input din of instance D4a is floating
@W:CL167 : Apple1Display.vhd(268) | Input din of instance D5b is floating
@W:CL167 : Apple1Display.vhd(267) | Input din of instance D5a is floating
@N:CD630 : master_clk.vhd(14) | Synthesizing work.master_clk.structure.
@N:CD630 : machxo2.vhd(2221) | Synthesizing work.ehxpllj.syn_black_box.
Post processing for work.ehxpllj.syn_black_box
Post processing for work.master_clk.structure
Post processing for work.fleafpga_uno_e1.arch
@N:CL201 : UART_RX.vhd(62) | Trying to extract state machine for register r_SM_Main.
Extracted state machine for register r_SM_Main
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL249 : UART_RX.vhd(62) | Initial value is not supported on state machine r_SM_Main
@N:CL189 : FleaFPGA_Uno_Top.vhd(165) | Register bit flash_count(23) is always 1.
@W:CL260 : FleaFPGA_Uno_Top.vhd(165) | Pruning register bit 23 of flash_count(23 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Aug  8 18:40:10 2019

###########################################################]
Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Aug  8 18:40:10 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Aug  8 18:40:10 2019

###########################################################]

Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
@N: :  | Running in 64-bit mode 
File C:\Dev\Apple1Display\impl1\synwork\impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Aug  8 18:40:12 2019

###########################################################]

Pre-mapping Report

# Thu Aug  8 18:40:12 2019

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 11:10:16
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version M-2017.03L-SP1-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
Linked File: impl1_scck.rpt
Printing clock  summary report in "C:\Dev\Apple1Display\impl1\impl1_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

@W:BN287 : dm74175.vhd(29) | Register states[3:0] with reset has an initial value of 1. Ignoring initial value.  
@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@W:BN287 : dm74174.vhd(34) | Register states[5:0] with reset has an initial value of 1. Ignoring initial value.  
@N:BN362 : uart_rx.vhd(62) | Removing sequential instance r_RX_Byte[7] (in view: work.UART_RX(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=26  set on top level netlist FleaFPGA_Uno_E1

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)



Clock Summary
******************

          Start                                  Requested     Requested     Clock                                          Clock                     Clock
Level     Clock                                  Frequency     Period        Type                                           Group                     Load 
-----------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                 1.0 MHz       1000.000      system                                         system_clkgroup           0    
                                                                                                                                                           
0 -       dm7427|y1_inferred_clock               259.2 MHz     3.858         inferred                                       Autoconstr_clkgroup_3     83   
                                                                                                                                                           
0 -       FleaFPGA_Uno_E1|sys_clock              236.1 MHz     4.236         inferred                                       Autoconstr_clkgroup_0     57   
                                                                                                                                                           
0 -       dm7400_1|y3_inferred_clock             483.5 MHz     2.068         inferred                                       Autoconstr_clkgroup_2     44   
                                                                                                                                                           
0 -       dm74175|q0_i_inferred_clock            1.0 MHz       1000.000      inferred                                       Autoconstr_clkgroup_5     13   
1 .         dm74161_4|count_derived_clock[3]     1.0 MHz       1000.000      derived (from dm74175|q0_i_inferred_clock)     Autoconstr_clkgroup_5     21   
                                                                                                                                                           
0 -       dm7400_1|y1_inferred_clock             329.3 MHz     3.037         inferred                                       Autoconstr_clkgroup_4     7    
                                                                                                                                                           
0 -       master_clk|CLKOS_inferred_clock        285.4 MHz     3.504         inferred                                       Autoconstr_clkgroup_1     6    
===========================================================================================================================================================

@W:MT529 : uart_rx.vhd(37) | Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : dm74175.vhd(29) | Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : dm74175.vhd(29) | Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : sig2504.vhd(187) | Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.D5a.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : shiftreg40.vhd(186) | Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : dm74175.vhd(29) | Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
original code -> new code
   00001 -> 000
   00010 -> 001
   00100 -> 010
   01000 -> 011
   10000 -> 100

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug  8 18:40:12 2019

###########################################################]

Map & Optimize Report

# Thu Aug  8 18:40:13 2019

Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 11:10:16
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version M-2017.03L-SP1-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@N:FX493 :  | Applying initial value "00000000" on instance uart_module.r_RX_Byte[7:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)

@N:BN362 : fleafpga_uno_top.vhd(165) | Removing sequential instance flash_count[22] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
@N:MO231 : dm74160.vhd(25) | Found counter in view:work.apple1display(behavior) instance D6.count[3:0] 
@N:MO231 : dm74161.vhd(25) | Found counter in view:work.dm74161_3(behavior) instance count[3:0] 
@N:MO231 : dm74161.vhd(25) | Found counter in view:work.dm74161_2(behavior) instance count[3:0] 
@N:MO231 : dm74161.vhd(25) | Found counter in view:work.dm74161_1(behavior) instance count[3:0] 
@N:MO231 : dm74161.vhd(25) | Found counter in view:work.dm74161_0(behavior) instance count[3:0] 
Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
original code -> new code
   00001 -> 000
   00010 -> 001
   00100 -> 010
   01000 -> 011
   10000 -> 100

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)

@N:BN362 : dm74175.vhd(29) | Removing sequential instance apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
@A:BN291 : dm74175.vhd(29) | Boundary register apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 158MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -3.68ns		 197 /        99
   2		0h:00m:02s		    -3.68ns		 199 /        99
   3		0h:00m:02s		    -3.18ns		 199 /        99
   4		0h:00m:02s		    -3.18ns		 199 /        99
   5		0h:00m:02s		    -3.18ns		 199 /        99
@N:FX271 : dm74174.vhd(34) | Replicating instance apple_module.C7.states[5] (in view: work.FleaFPGA_Uno_E1(arch)) with 9 loads 1 time to improve timing.
@N:FX271 : dm74174.vhd(34) | Replicating instance apple_module.C7.states[3] (in view: work.FleaFPGA_Uno_E1(arch)) with 8 loads 1 time to improve timing.
@N:FX271 : dm74174.vhd(34) | Replicating instance apple_module.C7.states[1] (in view: work.FleaFPGA_Uno_E1(arch)) with 6 loads 1 time to improve timing.
Timing driven replication report
Added 3 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   6		0h:00m:02s		    -3.69ns		 206 /       102
   7		0h:00m:02s		    -3.60ns		 206 /       102
@N:FX271 : dm74161.vhd(25) | Replicating instance apple_module.D7.count[3] (in view: work.FleaFPGA_Uno_E1(arch)) with 11 loads 1 time to improve timing.
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication


   8		0h:00m:02s		    -2.91ns		 210 /       103
   9		0h:00m:02s		    -2.91ns		 210 /       103
  10		0h:00m:02s		    -2.91ns		 210 /       103
  11		0h:00m:02s		    -2.91ns		 210 /       103

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 158MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_6_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_5_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_4_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_3_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_2_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_1_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : fleafpga_uno_top.vhd(165) | Boundary register rd_0_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@W:MT453 :  | clock period is too long for clock dm7400_1|y3_inferred_clock, changing period from 40622.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 20311.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock dm7427|y1_inferred_clock, changing period from 40622.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 20311.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock dm7400_1|y1_inferred_clock, changing period from 40622.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 20311.0 ns to 10000.0 ns.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 157MB peak: 158MB)

@N:MT611 :  | Automatically generated clock master_clk|CLKOS_inferred_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock dm74175|q0_i_inferred_clock is not used and is being removed 
@N:MT617 :  | Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 54 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 135 clock pin(s) of sequential element(s)
0 instances converted, 135 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId0005        sys_clock           port                   54         flash_count[0] 
=======================================================================================
===================================================================================================================== Gated/Generated Clocks ======================================================================================================================
Clock Tree ID     Driving Element                            Drive Element Type     Fanout     Sample Instance                       Explanation                                                                                                                   
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        clock_module.PLLInst_0                     EHXPLLJ                36         apple_module.D1.Qd                    Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
ClockId0002        apple_module.C5.y1                         ORCALUT4               86         apple_module.C7.states[5]             Multiple clocks on instance from nets line_clock, vbl_i                                                                       
ClockId0003        apple_module.D10.y1                        ORCALUT4               7          apple_module.C3.LineBuffer.FF_0       No gated clock conversion method for cell cell:LUCENT.FD1P3IX                                                                 
ClockId0004        apple_module.D10.y3_inferred_clock_RNO     ORCALUT4               6          apple_module.D13.flash_counter[0]     No clocks found on inputs                                                                                                     
===================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 122MB peak: 158MB)

Writing Analyst data base C:\Dev\Apple1Display\impl1\synwork\impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 158MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\Dev\Apple1Display\impl1\impl1.edi 
M-2017.03L-SP1-1
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 159MB peak: 161MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 159MB peak: 161MB)

@W:MT246 : master_clk.vhd(109) | Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 6.27ns. Please declare a user-defined clock on object "p:sys_clock" 
@W:MT420 :  | Found inferred clock dm7427|y1_inferred_clock with period 3.42ns. Please declare a user-defined clock on object "n:apple_module.C5.y1" 
@W:MT420 :  | Found inferred clock dm7400_1|y1_inferred_clock with period 6.07ns. Please declare a user-defined clock on object "n:apple_module.D10.y1" 
@W:MT420 :  | Found inferred clock dm7400_1|y3_inferred_clock with period 3.18ns. Please declare a user-defined clock on object "n:apple_module.D10.y3" 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Aug  8 18:40:17 2019
#


Top view:               FleaFPGA_Uno_E1
Requested Frequency:    159.6 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -2.724

                               Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                 Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------------------
FleaFPGA_Uno_E1|sys_clock      159.6 MHz     135.7 MHz     6.265         7.371         -1.106     inferred     Autoconstr_clkgroup_0
dm7400_1|y1_inferred_clock     164.6 MHz     168.4 MHz     6.074         5.938         0.136      inferred     Autoconstr_clkgroup_4
dm7400_1|y3_inferred_clock     314.4 MHz     267.3 MHz     3.180         3.741         -0.561     inferred     Autoconstr_clkgroup_2
dm7427|y1_inferred_clock       292.6 MHz     249.0 MHz     3.418         4.016         -0.598     inferred     Autoconstr_clkgroup_3
System                         160.7 MHz     152.1 MHz     6.221         6.575         -0.354     system       system_clkgroup      
====================================================================================================================================





Clock Relationships
*******************

Clocks                                                  |    rise  to  rise    |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------
Starting                    Ending                      |  constraint  slack   |  constraint  slack   |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------
System                      System                      |  6.222       -0.354  |  No paths    -       |  No paths    -      |  No paths    -    
System                      dm7427|y1_inferred_clock    |  3.418       -1.066  |  No paths    -       |  No paths    -      |  No paths    -    
System                      dm7400_1|y1_inferred_clock  |  6.074       0.619   |  No paths    -       |  No paths    -      |  No paths    -    
FleaFPGA_Uno_E1|sys_clock   System                      |  6.265       -0.142  |  No paths    -       |  No paths    -      |  No paths    -    
FleaFPGA_Uno_E1|sys_clock   FleaFPGA_Uno_E1|sys_clock   |  6.265       -1.106  |  No paths    -       |  No paths    -      |  No paths    -    
FleaFPGA_Uno_E1|sys_clock   dm7427|y1_inferred_clock    |  Diff grp    -       |  No paths    -       |  No paths    -      |  No paths    -    
FleaFPGA_Uno_E1|sys_clock   dm7400_1|y1_inferred_clock  |  Diff grp    -       |  No paths    -       |  No paths    -      |  No paths    -    
dm7400_1|y3_inferred_clock  dm7400_1|y3_inferred_clock  |  No paths    -       |  3.180       -0.561  |  No paths    -      |  No paths    -    
dm7400_1|y3_inferred_clock  dm7400_1|y1_inferred_clock  |  No paths    -       |  No paths    -       |  No paths    -      |  Diff grp    -    
dm7427|y1_inferred_clock    System                      |  3.418       -2.724  |  No paths    -       |  No paths    -      |  No paths    -    
dm7427|y1_inferred_clock    FleaFPGA_Uno_E1|sys_clock   |  Diff grp    -       |  No paths    -       |  No paths    -      |  No paths    -    
dm7427|y1_inferred_clock    dm7427|y1_inferred_clock    |  3.418       -0.598  |  No paths    -       |  No paths    -      |  No paths    -    
dm7427|y1_inferred_clock    dm7400_1|y1_inferred_clock  |  Diff grp    -       |  No paths    -       |  No paths    -      |  No paths    -    
dm7400_1|y1_inferred_clock  System                      |  6.074       0.655   |  No paths    -       |  No paths    -      |  No paths    -    
dm7400_1|y1_inferred_clock  dm7400_1|y1_inferred_clock  |  6.074       0.136   |  No paths    -       |  No paths    -      |  No paths    -    
================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: FleaFPGA_Uno_E1|sys_clock
====================================



Starting Points with Worst Slack
********************************

                   Starting                                                             Arrival           
Instance           Reference                     Type        Pin     Net                Time        Slack 
                   Clock                                                                                  
----------------------------------------------------------------------------------------------------------
flash_count[1]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     Q       flash_count[1]     1.044       -1.106
flash_count[4]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     Q       flash_count[4]     1.044       -1.106
flash_count[0]     FleaFPGA_Uno_E1|sys_clock     FD1S3AX     Q       flash_count[0]     1.108       -0.153
rd[0]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     Q       rd[0]              1.108       -0.142
rd[1]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     Q       rd[1]              1.108       -0.142
rd[3]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     Q       rd[3]              1.108       -0.142
rd[4]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     Q       rd[4]              1.108       -0.142
rd[6]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     Q       rd[6]              1.204       -0.102
flash_count[2]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     Q       flash_count[2]     1.044       -0.089
flash_count[3]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     Q       flash_count[3]     1.044       -0.089
==========================================================================================================


Ending Points with Worst Slack
******************************

                   Starting                                                                              Required           
Instance           Reference                     Type        Pin     Net                                 Time         Slack 
                   Clock                                                                                                    
----------------------------------------------------------------------------------------------------------------------------
rd[0]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
rd[1]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
rd[2]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
rd[3]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
rd[4]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
rd[5]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
rd[6]              FleaFPGA_Uno_E1|sys_clock     FD1P3JX     PD      un1_flash_countlto14_0_RNIEVM51     5.462        -1.106
flash_count[1]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     SP      un1_flash_countlt22                 5.793        -0.854
flash_count[2]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     SP      un1_flash_countlt22                 5.793        -0.854
flash_count[3]     FleaFPGA_Uno_E1|sys_clock     FD1P3AX     SP      un1_flash_countlt22                 5.793        -0.854
============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.265
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      6.568
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.106

    Number of logic level(s):                5
    Starting point:                          flash_count[1] / Q
    Ending point:                            rd[0] / PD
    The start point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
    The end   point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
flash_count[1]                      FD1P3AX      Q        Out     1.044     1.044       -         
flash_count[1]                      Net          -        -       -         -           2         
un1_flash_countlto4_1               ORCALUT4     A        In      0.000     1.044       -         
un1_flash_countlto4_1               ORCALUT4     Z        Out     1.017     2.061       -         
un1_flash_countlto4_1               Net          -        -       -         -           1         
un1_flash_countlto4                 ORCALUT4     D        In      0.000     2.061       -         
un1_flash_countlto4                 ORCALUT4     Z        Out     1.017     3.077       -         
un1_flash_countlt9                  Net          -        -       -         -           1         
un1_flash_countlto14_d              ORCALUT4     C        In      0.000     3.077       -         
un1_flash_countlto14_d              ORCALUT4     Z        Out     1.017     4.094       -         
un1_flash_countlto14_d              Net          -        -       -         -           1         
un1_flash_countlto14_0              ORCALUT4     D        In      0.000     4.094       -         
un1_flash_countlto14_0              ORCALUT4     Z        Out     1.225     5.319       -         
un1_flash_countlt16                 Net          -        -       -         -           5         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     B        In      0.000     5.319       -         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     Z        Out     1.249     6.568       -         
un1_flash_countlto14_0_RNIEVM51     Net          -        -       -         -           7         
rd[0]                               FD1P3JX      PD       In      0.000     6.568       -         
==================================================================================================


Path information for path number 2: 
      Requested Period:                      6.265
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      6.568
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.106

    Number of logic level(s):                5
    Starting point:                          flash_count[4] / Q
    Ending point:                            rd[0] / PD
    The start point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
    The end   point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
flash_count[4]                      FD1P3AX      Q        Out     1.044     1.044       -         
flash_count[4]                      Net          -        -       -         -           2         
un1_flash_countlto4_1               ORCALUT4     B        In      0.000     1.044       -         
un1_flash_countlto4_1               ORCALUT4     Z        Out     1.017     2.061       -         
un1_flash_countlto4_1               Net          -        -       -         -           1         
un1_flash_countlto4                 ORCALUT4     D        In      0.000     2.061       -         
un1_flash_countlto4                 ORCALUT4     Z        Out     1.017     3.077       -         
un1_flash_countlt9                  Net          -        -       -         -           1         
un1_flash_countlto14_d              ORCALUT4     C        In      0.000     3.077       -         
un1_flash_countlto14_d              ORCALUT4     Z        Out     1.017     4.094       -         
un1_flash_countlto14_d              Net          -        -       -         -           1         
un1_flash_countlto14_0              ORCALUT4     D        In      0.000     4.094       -         
un1_flash_countlto14_0              ORCALUT4     Z        Out     1.225     5.319       -         
un1_flash_countlt16                 Net          -        -       -         -           5         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     B        In      0.000     5.319       -         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     Z        Out     1.249     6.568       -         
un1_flash_countlto14_0_RNIEVM51     Net          -        -       -         -           7         
rd[0]                               FD1P3JX      PD       In      0.000     6.568       -         
==================================================================================================


Path information for path number 3: 
      Requested Period:                      6.265
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      6.568
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.106

    Number of logic level(s):                5
    Starting point:                          flash_count[1] / Q
    Ending point:                            rd[6] / PD
    The start point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
    The end   point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
flash_count[1]                      FD1P3AX      Q        Out     1.044     1.044       -         
flash_count[1]                      Net          -        -       -         -           2         
un1_flash_countlto4_1               ORCALUT4     A        In      0.000     1.044       -         
un1_flash_countlto4_1               ORCALUT4     Z        Out     1.017     2.061       -         
un1_flash_countlto4_1               Net          -        -       -         -           1         
un1_flash_countlto4                 ORCALUT4     D        In      0.000     2.061       -         
un1_flash_countlto4                 ORCALUT4     Z        Out     1.017     3.077       -         
un1_flash_countlt9                  Net          -        -       -         -           1         
un1_flash_countlto14_d              ORCALUT4     C        In      0.000     3.077       -         
un1_flash_countlto14_d              ORCALUT4     Z        Out     1.017     4.094       -         
un1_flash_countlto14_d              Net          -        -       -         -           1         
un1_flash_countlto14_0              ORCALUT4     D        In      0.000     4.094       -         
un1_flash_countlto14_0              ORCALUT4     Z        Out     1.225     5.319       -         
un1_flash_countlt16                 Net          -        -       -         -           5         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     B        In      0.000     5.319       -         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     Z        Out     1.249     6.568       -         
un1_flash_countlto14_0_RNIEVM51     Net          -        -       -         -           7         
rd[6]                               FD1P3JX      PD       In      0.000     6.568       -         
==================================================================================================


Path information for path number 4: 
      Requested Period:                      6.265
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      6.568
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.106

    Number of logic level(s):                5
    Starting point:                          flash_count[1] / Q
    Ending point:                            rd[5] / PD
    The start point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
    The end   point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
flash_count[1]                      FD1P3AX      Q        Out     1.044     1.044       -         
flash_count[1]                      Net          -        -       -         -           2         
un1_flash_countlto4_1               ORCALUT4     A        In      0.000     1.044       -         
un1_flash_countlto4_1               ORCALUT4     Z        Out     1.017     2.061       -         
un1_flash_countlto4_1               Net          -        -       -         -           1         
un1_flash_countlto4                 ORCALUT4     D        In      0.000     2.061       -         
un1_flash_countlto4                 ORCALUT4     Z        Out     1.017     3.077       -         
un1_flash_countlt9                  Net          -        -       -         -           1         
un1_flash_countlto14_d              ORCALUT4     C        In      0.000     3.077       -         
un1_flash_countlto14_d              ORCALUT4     Z        Out     1.017     4.094       -         
un1_flash_countlto14_d              Net          -        -       -         -           1         
un1_flash_countlto14_0              ORCALUT4     D        In      0.000     4.094       -         
un1_flash_countlto14_0              ORCALUT4     Z        Out     1.225     5.319       -         
un1_flash_countlt16                 Net          -        -       -         -           5         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     B        In      0.000     5.319       -         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     Z        Out     1.249     6.568       -         
un1_flash_countlto14_0_RNIEVM51     Net          -        -       -         -           7         
rd[5]                               FD1P3JX      PD       In      0.000     6.568       -         
==================================================================================================


Path information for path number 5: 
      Requested Period:                      6.265
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      6.568
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.106

    Number of logic level(s):                5
    Starting point:                          flash_count[1] / Q
    Ending point:                            rd[4] / PD
    The start point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
    The end   point is clocked by            FleaFPGA_Uno_E1|sys_clock [rising] on pin CK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
flash_count[1]                      FD1P3AX      Q        Out     1.044     1.044       -         
flash_count[1]                      Net          -        -       -         -           2         
un1_flash_countlto4_1               ORCALUT4     A        In      0.000     1.044       -         
un1_flash_countlto4_1               ORCALUT4     Z        Out     1.017     2.061       -         
un1_flash_countlto4_1               Net          -        -       -         -           1         
un1_flash_countlto4                 ORCALUT4     D        In      0.000     2.061       -         
un1_flash_countlto4                 ORCALUT4     Z        Out     1.017     3.077       -         
un1_flash_countlt9                  Net          -        -       -         -           1         
un1_flash_countlto14_d              ORCALUT4     C        In      0.000     3.077       -         
un1_flash_countlto14_d              ORCALUT4     Z        Out     1.017     4.094       -         
un1_flash_countlto14_d              Net          -        -       -         -           1         
un1_flash_countlto14_0              ORCALUT4     D        In      0.000     4.094       -         
un1_flash_countlto14_0              ORCALUT4     Z        Out     1.225     5.319       -         
un1_flash_countlt16                 Net          -        -       -         -           5         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     B        In      0.000     5.319       -         
un1_flash_countlto14_0_RNIEVM51     ORCALUT4     Z        Out     1.249     6.568       -         
un1_flash_countlto14_0_RNIEVM51     Net          -        -       -         -           7         
rd[4]                               FD1P3JX      PD       In      0.000     6.568       -         
==================================================================================================




====================================
Detailed Report for Clock: dm7400_1|y1_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                            Starting                                                               Arrival          
Instance                                    Reference                      Type        Pin      Net                Time        Slack
                                            Clock                                                                                   
------------------------------------------------------------------------------------------------------------------------------------
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC       DOA0     screen_char[0]     3.737       0.136
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC       DOA1     screen_char[1]     3.737       0.136
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC       DOA2     screen_char[2]     3.737       0.136
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC       DOA3     screen_char[3]     3.737       0.136
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC       DOA4     screen_char[4]     3.737       0.136
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC       DOA5     screen_char[5]     3.737       0.136
apple_module.C3.LineBuffer.FF_2             dm7400_1|y1_inferred_clock     FD1P3IX     Q        shreg_addr_w3      1.108       2.365
apple_module.C3.LineBuffer.FF_5             dm7400_1|y1_inferred_clock     FD1P3IX     Q        shreg_addr_w0      1.108       2.365
apple_module.C3.LineBuffer.FF_3             dm7400_1|y1_inferred_clock     FD1P3IX     Q        shreg_addr_w2      1.108       2.933
apple_module.C3.LineBuffer.FF_4             dm7400_1|y1_inferred_clock     FD1P3IX     Q        shreg_addr_w1      1.108       2.933
====================================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                                              Required          
Instance                                    Reference                      Type      Pin       Net                Time         Slack
                                            Clock                                                                                   
------------------------------------------------------------------------------------------------------------------------------------
apple_module.D2.sig2513_0_0_0               dm7400_1|y1_inferred_clock     DP8KC     ADA6      screen_char[0]     4.392        0.655
apple_module.D2.sig2513_0_0_0               dm7400_1|y1_inferred_clock     DP8KC     ADA7      screen_char[1]     4.392        0.655
apple_module.D2.sig2513_0_0_0               dm7400_1|y1_inferred_clock     DP8KC     ADA8      screen_char[2]     4.392        0.655
apple_module.D2.sig2513_0_0_0               dm7400_1|y1_inferred_clock     DP8KC     ADA9      screen_char[3]     4.392        0.655
apple_module.D2.sig2513_0_0_0               dm7400_1|y1_inferred_clock     DP8KC     ADA10     screen_char[4]     4.392        0.655
apple_module.D2.sig2513_0_0_0               dm7400_1|y1_inferred_clock     DP8KC     ADA11     screen_char[5]     4.392        0.655
apple_module.C3.LineBuffer.OR2_t0           dm7400_1|y1_inferred_clock     OR2       B         dec0_r102          6.074        2.365
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC     ADA3      shreg_addr_w0      4.392        3.284
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC     ADA4      shreg_addr_w1      4.392        3.284
apple_module.C3.LineBuffer.sram_1_0_0_0     dm7400_1|y1_inferred_clock     DP8KC     ADA5      shreg_addr_w2      4.392        3.284
====================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.074
    - Setup time:                            1.753
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.321

    - Propagation time:                      4.185
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.136

    Number of logic level(s):                1
    Starting point:                          apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA0
    Ending point:                            apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA0
    The start point is clocked by            dm7400_1|y1_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            dm7400_1|y1_inferred_clock [rising] on pin CLKA

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                        Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
apple_module.C3.LineBuffer.sram_1_0_0_0     DP8KC        DOA0     Out     3.737     3.737       -         
screen_char[0]                              Net          -        -       -         -           2         
apple_module.C3.input[0]                    ORCALUT4     D        In      0.000     3.737       -         
apple_module.C3.input[0]                    ORCALUT4     Z        Out     0.449     4.185       -         
input[0]                                    Net          -        -       -         -           1         
apple_module.C3.LineBuffer.sram_1_0_0_0     DP8KC        DIA0     In      0.000     4.185       -         
==========================================================================================================




====================================
Detailed Report for Clock: dm7400_1|y3_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                                Arrival           
Instance                              Reference                      Type        Pin     Net                  Time        Slack 
                                      Clock                                                                                     
--------------------------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[2]     dm7400_1|y3_inferred_clock     FD1S3AX     Q       flash_counter[2]     1.180       -0.561
apple_module.D13.flash_counter[4]     dm7400_1|y3_inferred_clock     FD1S3AX     Q       flash_counter[4]     1.180       -0.561
apple_module.D13.flash_counter[3]     dm7400_1|y3_inferred_clock     FD1S3AX     Q       flash_counter[3]     1.148       -0.529
apple_module.D13.flash_counter[0]     dm7400_1|y3_inferred_clock     FD1S3AX     Q       flash_counter[0]     1.188       0.376 
apple_module.D13.flash_counter[1]     dm7400_1|y3_inferred_clock     FD1S3AX     Q       flash_counter[1]     1.188       0.376 
apple_module.D13.flash_counter[5]     dm7400_1|y3_inferred_clock     FD1S3AX     Q       cursor_flash         1.108       0.528 
================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                                          Required           
Instance                              Reference                      Type        Pin     Net                            Time         Slack 
                                      Clock                                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[5]     dm7400_1|y3_inferred_clock     FD1S3AX     D       flash_counter_3[5]             3.269        -0.561
apple_module.D13.flash_counter[4]     dm7400_1|y3_inferred_clock     FD1S3AX     D       un3_flash_counter_1_axbxc4     3.269        0.376 
apple_module.D13.flash_counter[0]     dm7400_1|y3_inferred_clock     FD1S3AX     D       flash_counter_3[0]             3.269        0.448 
apple_module.D13.flash_counter[1]     dm7400_1|y3_inferred_clock     FD1S3AX     D       un3_flash_counter_1_axbxc1     3.269        1.464 
apple_module.D13.flash_counter[2]     dm7400_1|y3_inferred_clock     FD1S3AX     D       un3_flash_counter_1_axbxc2     3.269        1.464 
apple_module.D13.flash_counter[3]     dm7400_1|y3_inferred_clock     FD1S3AX     D       un3_flash_counter_1_axbxc3     3.269        1.464 
===========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      3.180
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.269

    - Propagation time:                      3.830
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.561

    Number of logic level(s):                3
    Starting point:                          apple_module.D13.flash_counter[2] / Q
    Ending point:                            apple_module.D13.flash_counter[5] / D
    The start point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK
    The end   point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[2]                  FD1S3AX      Q        Out     1.180     1.180       -         
flash_counter[2]                                   Net          -        -       -         -           5         
apple_module.D13.flash_counter_3_N_3L3_0_N_2L1     ORCALUT4     A        In      0.000     1.180       -         
apple_module.D13.flash_counter_3_N_3L3_0_N_2L1     ORCALUT4     Z        Out     1.017     2.197       -         
flash_counter_3_N_3L3_0_N_2L1                      Net          -        -       -         -           1         
apple_module.D13.flash_counter_3_N_3L3_0           ORCALUT4     D        In      0.000     2.197       -         
apple_module.D13.flash_counter_3_N_3L3_0           ORCALUT4     Z        Out     1.017     3.213       -         
flash_counter_3_N_3L3_0                            Net          -        -       -         -           1         
apple_module.D13.flash_counter_3[5]                ORCALUT4     B        In      0.000     3.213       -         
apple_module.D13.flash_counter_3[5]                ORCALUT4     Z        Out     0.617     3.830       -         
flash_counter_3[5]                                 Net          -        -       -         -           1         
apple_module.D13.flash_counter[5]                  FD1S3AX      D        In      0.000     3.830       -         
=================================================================================================================


Path information for path number 2: 
      Requested Period:                      3.180
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.269

    - Propagation time:                      3.830
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.561

    Number of logic level(s):                3
    Starting point:                          apple_module.D13.flash_counter[4] / Q
    Ending point:                            apple_module.D13.flash_counter[5] / D
    The start point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK
    The end   point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[4]                  FD1S3AX      Q        Out     1.180     1.180       -         
flash_counter[4]                                   Net          -        -       -         -           5         
apple_module.D13.flash_counter_3_N_3L3_0_N_2L1     ORCALUT4     C        In      0.000     1.180       -         
apple_module.D13.flash_counter_3_N_3L3_0_N_2L1     ORCALUT4     Z        Out     1.017     2.197       -         
flash_counter_3_N_3L3_0_N_2L1                      Net          -        -       -         -           1         
apple_module.D13.flash_counter_3_N_3L3_0           ORCALUT4     D        In      0.000     2.197       -         
apple_module.D13.flash_counter_3_N_3L3_0           ORCALUT4     Z        Out     1.017     3.213       -         
flash_counter_3_N_3L3_0                            Net          -        -       -         -           1         
apple_module.D13.flash_counter_3[5]                ORCALUT4     B        In      0.000     3.213       -         
apple_module.D13.flash_counter_3[5]                ORCALUT4     Z        Out     0.617     3.830       -         
flash_counter_3[5]                                 Net          -        -       -         -           1         
apple_module.D13.flash_counter[5]                  FD1S3AX      D        In      0.000     3.830       -         
=================================================================================================================


Path information for path number 3: 
      Requested Period:                      3.180
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.269

    - Propagation time:                      3.798
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.529

    Number of logic level(s):                3
    Starting point:                          apple_module.D13.flash_counter[3] / Q
    Ending point:                            apple_module.D13.flash_counter[5] / D
    The start point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK
    The end   point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[3]                  FD1S3AX      Q        Out     1.148     1.148       -         
flash_counter[3]                                   Net          -        -       -         -           4         
apple_module.D13.flash_counter_3_N_3L3_0_N_2L1     ORCALUT4     B        In      0.000     1.148       -         
apple_module.D13.flash_counter_3_N_3L3_0_N_2L1     ORCALUT4     Z        Out     1.017     2.165       -         
flash_counter_3_N_3L3_0_N_2L1                      Net          -        -       -         -           1         
apple_module.D13.flash_counter_3_N_3L3_0           ORCALUT4     D        In      0.000     2.165       -         
apple_module.D13.flash_counter_3_N_3L3_0           ORCALUT4     Z        Out     1.017     3.181       -         
flash_counter_3_N_3L3_0                            Net          -        -       -         -           1         
apple_module.D13.flash_counter_3[5]                ORCALUT4     B        In      0.000     3.181       -         
apple_module.D13.flash_counter_3[5]                ORCALUT4     Z        Out     0.617     3.798       -         
flash_counter_3[5]                                 Net          -        -       -         -           1         
apple_module.D13.flash_counter[5]                  FD1S3AX      D        In      0.000     3.798       -         
=================================================================================================================


Path information for path number 4: 
      Requested Period:                      3.180
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.269

    - Propagation time:                      2.893
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.376

    Number of logic level(s):                2
    Starting point:                          apple_module.D13.flash_counter[0] / Q
    Ending point:                            apple_module.D13.flash_counter[5] / D
    The start point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK
    The end   point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[0]              FD1S3AX      Q        Out     1.188     1.188       -         
flash_counter[0]                               Net          -        -       -         -           6         
apple_module.D13.un3_flash_counter_1_ac0_1     ORCALUT4     A        In      0.000     1.188       -         
apple_module.D13.un3_flash_counter_1_ac0_1     ORCALUT4     Z        Out     1.089     2.277       -         
un3_flash_counter_1_c2                         Net          -        -       -         -           2         
apple_module.D13.flash_counter_3[5]            ORCALUT4     C        In      0.000     2.277       -         
apple_module.D13.flash_counter_3[5]            ORCALUT4     Z        Out     0.617     2.893       -         
flash_counter_3[5]                             Net          -        -       -         -           1         
apple_module.D13.flash_counter[5]              FD1S3AX      D        In      0.000     2.893       -         
=============================================================================================================


Path information for path number 5: 
      Requested Period:                      3.180
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.269

    - Propagation time:                      2.893
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.376

    Number of logic level(s):                2
    Starting point:                          apple_module.D13.flash_counter[1] / Q
    Ending point:                            apple_module.D13.flash_counter[5] / D
    The start point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK
    The end   point is clocked by            dm7400_1|y3_inferred_clock [falling] on pin CK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
apple_module.D13.flash_counter[1]              FD1S3AX      Q        Out     1.188     1.188       -         
flash_counter[1]                               Net          -        -       -         -           6         
apple_module.D13.un3_flash_counter_1_ac0_1     ORCALUT4     B        In      0.000     1.188       -         
apple_module.D13.un3_flash_counter_1_ac0_1     ORCALUT4     Z        Out     1.089     2.277       -         
un3_flash_counter_1_c2                         Net          -        -       -         -           2         
apple_module.D13.flash_counter_3[5]            ORCALUT4     C        In      0.000     2.277       -         
apple_module.D13.flash_counter_3[5]            ORCALUT4     Z        Out     0.617     2.893       -         
flash_counter_3[5]                             Net          -        -       -         -           1         
apple_module.D13.flash_counter[5]              FD1S3AX      D        In      0.000     2.893       -         
=============================================================================================================




====================================
Detailed Report for Clock: dm7427|y1_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                   Starting                                                                   Arrival           
Instance                           Reference                    Type        Pin      Net                      Time        Slack 
                                   Clock                                                                                        
--------------------------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]          dm7427|y1_inferred_clock     FD1S3AX     Q        wc2_i                    1.220       -2.724
apple_module.C7.states[3]          dm7427|y1_inferred_clock     FD1S3AX     Q        cleared_last             1.188       -2.692
apple_module.C7.states[0]          dm7427|y1_inferred_clock     FD1S3AX     Q        screen_clear_inhibit     1.232       -2.585
apple_module.C7.states[1]          dm7427|y1_inferred_clock     FD1S3AX     Q        char_ready               1.204       -2.500
apple_module.C7.states_fast[3]     dm7427|y1_inferred_clock     FD1S3AX     Q        states_fast[3]           1.108       -1.836
apple_module.C7.states[4]          dm7427|y1_inferred_clock     FD1S3AX     Q        line_clear_inhibit       1.044       -1.772
apple_module.C7.states_fast[5]     dm7427|y1_inferred_clock     FD1S3AX     Q        states_fast[5]           1.044       -1.772
apple_module.C7.states_fast[1]     dm7427|y1_inferred_clock     FD1S3AX     Q        states_fast[1]           0.972       -1.700
apple_module.C11b.sram_1_0_0_0     dm7427|y1_inferred_clock     DP8KC       DOA0     mem_curs_out[0]          3.737       -0.424
apple_module.C11b.FF_9             dm7427|y1_inferred_clock     FD1P3IX     Q        shreg_addr_w0            1.108       -0.291
================================================================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                                             Required           
Instance                           Reference                    Type        Pin     Net                 Time         Slack 
                                   Clock                                                                                   
---------------------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]          dm7427|y1_inferred_clock     FD1S3AX     D       wc1_i               3.313        -0.598
apple_module.C7.states_fast[5]     dm7427|y1_inferred_clock     FD1S3AX     D       wc1_i_fast          3.313        -0.598
apple_module.C13.states[3]         dm7427|y1_inferred_clock     FD1S3AX     D       mem_curs_out[0]     3.313        -0.424
apple_module.C11b.OR2_t0           dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
apple_module.D4a.OR2_t0            dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
apple_module.D14b.OR2_t0           dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
apple_module.D14a.OR2_t0           dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
apple_module.D4b.OR2_t0            dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
apple_module.D5a.OR2_t0            dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
apple_module.D5b.OR2_t0            dm7427|y1_inferred_clock     OR2         B       dec0_r2046          3.418        -0.291
===========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      3.418
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         2.947

    - Propagation time:                      5.671
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.724

    Number of logic level(s):                4
    Starting point:                          apple_module.C7.states[5] / Q
    Ending point:                            apple_module.D8.count[0] / SP
    The start point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]                     FD1S3AX      Q        Out     1.220     1.220       -         
wc2_i                                         Net          -        -       -         -           8         
apple_module.C12.g0_1                         ORCALUT4     C        In      0.000     1.220       -         
apple_module.C12.g0_1                         ORCALUT4     Z        Out     1.017     2.237       -         
g0_1                                          Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     C        In      0.000     2.237       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.461       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     B        In      0.000     3.461       -         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     Z        Out     1.017     4.478       -         
count_cnv_x0[0]                               Net          -        -       -         -           1         
apple_module.D8.count_cnv[0]                  ORCALUT4     A        In      0.000     4.478       -         
apple_module.D8.count_cnv[0]                  ORCALUT4     Z        Out     1.193     5.671       -         
count_cnv_0[0]                                Net          -        -       -         -           4         
apple_module.D8.count[0]                      FD1P3DX      SP       In      0.000     5.671       -         
============================================================================================================


Path information for path number 2: 
      Requested Period:                      3.418
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         2.947

    - Propagation time:                      5.671
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.724

    Number of logic level(s):                4
    Starting point:                          apple_module.C7.states[5] / Q
    Ending point:                            apple_module.D8.count[3] / SP
    The start point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]                     FD1S3AX      Q        Out     1.220     1.220       -         
wc2_i                                         Net          -        -       -         -           8         
apple_module.C12.g0_1                         ORCALUT4     C        In      0.000     1.220       -         
apple_module.C12.g0_1                         ORCALUT4     Z        Out     1.017     2.237       -         
g0_1                                          Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     C        In      0.000     2.237       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.461       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     B        In      0.000     3.461       -         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     Z        Out     1.017     4.478       -         
count_cnv_x0[0]                               Net          -        -       -         -           1         
apple_module.D8.count_cnv[0]                  ORCALUT4     A        In      0.000     4.478       -         
apple_module.D8.count_cnv[0]                  ORCALUT4     Z        Out     1.193     5.671       -         
count_cnv_0[0]                                Net          -        -       -         -           4         
apple_module.D8.count[3]                      FD1P3DX      SP       In      0.000     5.671       -         
============================================================================================================


Path information for path number 3: 
      Requested Period:                      3.418
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         2.947

    - Propagation time:                      5.671
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.724

    Number of logic level(s):                4
    Starting point:                          apple_module.C7.states[5] / Q
    Ending point:                            apple_module.D8.count[2] / SP
    The start point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]                     FD1S3AX      Q        Out     1.220     1.220       -         
wc2_i                                         Net          -        -       -         -           8         
apple_module.C12.g0_1                         ORCALUT4     C        In      0.000     1.220       -         
apple_module.C12.g0_1                         ORCALUT4     Z        Out     1.017     2.237       -         
g0_1                                          Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     C        In      0.000     2.237       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.461       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     B        In      0.000     3.461       -         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     Z        Out     1.017     4.478       -         
count_cnv_x0[0]                               Net          -        -       -         -           1         
apple_module.D8.count_cnv[0]                  ORCALUT4     A        In      0.000     4.478       -         
apple_module.D8.count_cnv[0]                  ORCALUT4     Z        Out     1.193     5.671       -         
count_cnv_0[0]                                Net          -        -       -         -           4         
apple_module.D8.count[2]                      FD1P3DX      SP       In      0.000     5.671       -         
============================================================================================================


Path information for path number 4: 
      Requested Period:                      3.418
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         2.947

    - Propagation time:                      5.671
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.724

    Number of logic level(s):                4
    Starting point:                          apple_module.C7.states[5] / Q
    Ending point:                            apple_module.D8.count[1] / SP
    The start point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]                     FD1S3AX      Q        Out     1.220     1.220       -         
wc2_i                                         Net          -        -       -         -           8         
apple_module.C12.g0_1                         ORCALUT4     C        In      0.000     1.220       -         
apple_module.C12.g0_1                         ORCALUT4     Z        Out     1.017     2.237       -         
g0_1                                          Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     C        In      0.000     2.237       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.461       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     B        In      0.000     3.461       -         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     Z        Out     1.017     4.478       -         
count_cnv_x0[0]                               Net          -        -       -         -           1         
apple_module.D8.count_cnv[0]                  ORCALUT4     A        In      0.000     4.478       -         
apple_module.D8.count_cnv[0]                  ORCALUT4     Z        Out     1.193     5.671       -         
count_cnv_0[0]                                Net          -        -       -         -           4         
apple_module.D8.count[1]                      FD1P3DX      SP       In      0.000     5.671       -         
============================================================================================================


Path information for path number 5: 
      Requested Period:                      3.418
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         2.947

    - Propagation time:                      5.639
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.692

    Number of logic level(s):                4
    Starting point:                          apple_module.C7.states[3] / Q
    Ending point:                            apple_module.D8.count[0] / SP
    The start point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C7.states[3]                     FD1S3AX      Q        Out     1.188     1.188       -         
cleared_last                                  Net          -        -       -         -           6         
apple_module.C12.g0_1                         ORCALUT4     B        In      0.000     1.188       -         
apple_module.C12.g0_1                         ORCALUT4     Z        Out     1.017     2.205       -         
g0_1                                          Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     C        In      0.000     2.205       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.429       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     B        In      0.000     3.429       -         
apple_module.D8.count_cnv_x0[0]               ORCALUT4     Z        Out     1.017     4.446       -         
count_cnv_x0[0]                               Net          -        -       -         -           1         
apple_module.D8.count_cnv[0]                  ORCALUT4     A        In      0.000     4.446       -         
apple_module.D8.count_cnv[0]                  ORCALUT4     Z        Out     1.193     5.639       -         
count_cnv_0[0]                                Net          -        -       -         -           4         
apple_module.D8.count[0]                      FD1P3DX      SP       In      0.000     5.639       -         
============================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                  Arrival           
Instance                          Reference     Type        Pin     Net                     Time        Slack 
                                  Clock                                                                       
--------------------------------------------------------------------------------------------------------------
apple_module.C13.states[3]        System        FD1S3AX     Q       states[3]               1.232       -1.066
apple_module.D6.count[3]          System        FD1P3AX     Q       horz_count_lower[3]     1.204       -0.354
apple_module.D9.count[2]          System        FD1P3DX     Q       count[2]                1.148       -0.338
apple_module.D6.count[1]          System        FD1P3AX     Q       count[1]                1.148       -0.298
apple_module.D6.count[2]          System        FD1P3AX     Q       count[2]                1.148       -0.298
apple_module.D9.count[3]          System        FD1P3DX     Q       count[3]                1.108       -0.297
apple_module.D7.count_fast[3]     System        FD1P3AX     Q       count_fast[3]           1.044       -0.234
apple_module.D7.count[3]          System        FD1P3AX     Q       horz_count_upper[3]     1.236       -0.178
apple_module.D7.count[2]          System        FD1P3AX     Q       horz_count_upper[2]     1.232       -0.174
apple_module.D7.count[1]          System        FD1P3AX     Q       count[1]                1.220       -0.162
==============================================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                               Required           
Instance                           Reference     Type        Pin      Net                 Time         Slack 
                                   Clock                                                                     
-------------------------------------------------------------------------------------------------------------
apple_module.C7.states[5]          System        FD1S3AX     D        wc1_i               3.313        -1.066
apple_module.C7.states_fast[5]     System        FD1S3AX     D        wc1_i_fast          3.313        -1.066
apple_module.C7.states[0]          System        FD1S3AX     D        last                3.313        -0.014
apple_module.C11b.sram_1_0_0_0     System        DP8KC       DIA1     mem_curs_in[0]      1.666        0.245 
apple_module.C7.states[3]          System        FD1S3AX     D        clear_char          3.313        0.407 
apple_module.C7.states_fast[3]     System        FD1S3AX     D        clear_char_fast     3.313        0.407 
apple_module.C7.states[4]          System        FD1S3AX     D        last_h              3.313        0.435 
apple_module.C7.states[2]          System        FD1S3AX     D        y2_i                3.313        1.632 
apple_module.D1.Qd                 System        FD1P3AX     D        Qd_3                6.310        1.957 
apple_module.D1.Qe                 System        FD1P3AX     D        Qe_3                6.310        1.957 
=============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      3.418
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.313

    - Propagation time:                      4.379
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.066

    Number of logic level(s):                4
    Starting point:                          apple_module.C13.states[3] / Q
    Ending point:                            apple_module.C7.states[5] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
apple_module.C13.states[3]      FD1S3AX      Q        Out     1.232     1.232       -         
states[3]                       Net          -        -       -         -           10        
apple_module.C8.un1_m1_e_0      ORCALUT4     A        In      0.000     1.232       -         
apple_module.C8.un1_m1_e_0      ORCALUT4     Z        Out     1.017     2.249       -         
un1_m1_e_0                      Net          -        -       -         -           1         
apple_module.C8.un1_m2_0_a2     ORCALUT4     D        In      0.000     2.249       -         
apple_module.C8.un1_m2_0_a2     ORCALUT4     Z        Out     0.449     2.697       -         
un1_N_5_mux                     Net          -        -       -         -           3         
apple_module.C12.g0_0           ORCALUT4     C        In      0.000     2.697       -         
apple_module.C12.g0_0           ORCALUT4     Z        Out     1.233     3.930       -         
un8_y1                          Net          -        -       -         -           6         
apple_module.C12.Y2_0           ORCALUT4     A        In      0.000     3.930       -         
apple_module.C12.Y2_0           ORCALUT4     Z        Out     0.449     4.379       -         
wc1_i                           Net          -        -       -         -           1         
apple_module.C7.states[5]       FD1S3AX      D        In      0.000     4.379       -         
==============================================================================================


Path information for path number 2: 
      Requested Period:                      3.418
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.313

    - Propagation time:                      4.379
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.066

    Number of logic level(s):                4
    Starting point:                          apple_module.C13.states[3] / Q
    Ending point:                            apple_module.C7.states_fast[5] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                               Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
apple_module.C13.states[3]         FD1S3AX      Q        Out     1.232     1.232       -         
states[3]                          Net          -        -       -         -           10        
apple_module.C8.un1_m1_e_0         ORCALUT4     A        In      0.000     1.232       -         
apple_module.C8.un1_m1_e_0         ORCALUT4     Z        Out     1.017     2.249       -         
un1_m1_e_0                         Net          -        -       -         -           1         
apple_module.C8.un1_m2_0_a2        ORCALUT4     D        In      0.000     2.249       -         
apple_module.C8.un1_m2_0_a2        ORCALUT4     Z        Out     0.449     2.697       -         
un1_N_5_mux                        Net          -        -       -         -           3         
apple_module.C12.g0_0              ORCALUT4     C        In      0.000     2.697       -         
apple_module.C12.g0_0              ORCALUT4     Z        Out     1.233     3.930       -         
un8_y1                             Net          -        -       -         -           6         
apple_module.C12.Y2_0_fast         ORCALUT4     A        In      0.000     3.930       -         
apple_module.C12.Y2_0_fast         ORCALUT4     Z        Out     0.449     4.379       -         
wc1_i_fast                         Net          -        -       -         -           1         
apple_module.C7.states_fast[5]     FD1S3AX      D        In      0.000     4.379       -         
=================================================================================================


Path information for path number 3: 
      Requested Period:                      3.418
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.313

    - Propagation time:                      3.922
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.610

    Number of logic level(s):                3
    Starting point:                          apple_module.C13.states[3] / Q
    Ending point:                            apple_module.C7.states[5] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C13.states[3]                    FD1S3AX      Q        Out     1.232     1.232       -         
states[3]                                     Net          -        -       -         -           10        
apple_module.C12.Y2_m1_e_0_N_2L1              ORCALUT4     A        In      0.000     1.232       -         
apple_module.C12.Y2_m1_e_0_N_2L1              ORCALUT4     Z        Out     1.017     2.249       -         
Y2_m1_e_0_N_2L1                               Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     A        In      0.000     2.249       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.473       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.C12.Y2_0                         ORCALUT4     B        In      0.000     3.473       -         
apple_module.C12.Y2_0                         ORCALUT4     Z        Out     0.449     3.922       -         
wc1_i                                         Net          -        -       -         -           1         
apple_module.C7.states[5]                     FD1S3AX      D        In      0.000     3.922       -         
============================================================================================================


Path information for path number 4: 
      Requested Period:                      3.418
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.313

    - Propagation time:                      3.922
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.610

    Number of logic level(s):                3
    Starting point:                          apple_module.C13.states[3] / Q
    Ending point:                            apple_module.C7.states_fast[5] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            dm7427|y1_inferred_clock [rising] on pin CK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                          Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
apple_module.C13.states[3]                    FD1S3AX      Q        Out     1.232     1.232       -         
states[3]                                     Net          -        -       -         -           10        
apple_module.C12.Y2_m1_e_0_N_2L1              ORCALUT4     A        In      0.000     1.232       -         
apple_module.C12.Y2_m1_e_0_N_2L1              ORCALUT4     Z        Out     1.017     2.249       -         
Y2_m1_e_0_N_2L1                               Net          -        -       -         -           1         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     A        In      0.000     2.249       -         
apple_module.C12.Y2_m1_e_0_N_2L1_RNID0SD1     ORCALUT4     Z        Out     1.225     3.473       -         
Y2_m1_e_0_N_2L1_RNID0SD1                      Net          -        -       -         -           5         
apple_module.C12.Y2_0_fast                    ORCALUT4     B        In      0.000     3.473       -         
apple_module.C12.Y2_0_fast                    ORCALUT4     Z        Out     0.449     3.922       -         
wc1_i_fast                                    Net          -        -       -         -           1         
apple_module.C7.states_fast[5]                FD1S3AX      D        In      0.000     3.922       -         
============================================================================================================


Path information for path number 5: 
      Requested Period:                      6.221
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         5.750

    - Propagation time:                      6.104
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.354

    Number of logic level(s):                5
    Starting point:                          apple_module.D6.count[3] / Q
    Ending point:                            apple_module.D8.count[0] / SP
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                       Pin      Pin               Arrival     No. of    
Name                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------
apple_module.D6.count[3]                FD1P3AX      Q        Out     1.204     1.204       -         
horz_count_lower[3]                     Net          -        -       -         -           7         
apple_module.D6.count_RNI0Q761[1]       ORCALUT4     C        In      0.000     1.204       -         
apple_module.D6.count_RNI0Q761[1]       ORCALUT4     Z        Out     1.225     2.429       -         
N_66                                    Net          -        -       -         -           5         
apple_module.D7.count_RNI0GGQ1[0]       ORCALUT4     A        In      0.000     2.429       -         
apple_module.D7.count_RNI0GGQ1[0]       ORCALUT4     Z        Out     0.449     2.877       -         
last_h                                  Net          -        -       -         -           4         
apple_module.D8.count_cnv_0_N_3L3_0     ORCALUT4     A        In      0.000     2.877       -         
apple_module.D8.count_cnv_0_N_3L3_0     ORCALUT4     Z        Out     1.017     3.894       -         
count_cnv_0_N_3L3_0                     Net          -        -       -         -           1         
apple_module.D8.count_cnv_0[0]          ORCALUT4     C        In      0.000     3.894       -         
apple_module.D8.count_cnv_0[0]          ORCALUT4     Z        Out     1.017     4.911       -         
count_cnv_0_0[0]                        Net          -        -       -         -           1         
apple_module.D8.count_cnv[0]            ORCALUT4     B        In      0.000     4.911       -         
apple_module.D8.count_cnv[0]            ORCALUT4     Z        Out     1.193     6.104       -         
count_cnv_0[0]                          Net          -        -       -         -           4         
apple_module.D8.count[0]                FD1P3DX      SP       In      0.000     6.104       -         
======================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 159MB peak: 161MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 159MB peak: 161MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_7000hc-4

Register bits: 179 of 6864 (3%)
PIC Latch:       0
I/O cells:       15
Block Rams : 9 of 26 (34%)


Details:
CCU2D:          12
CU2:            38
DP8KC:          9
FADD2B:         8
FD1P3AX:        50
FD1P3DX:        8
FD1P3IX:        76
FD1P3JX:        7
FD1S3AX:        28
FD1S3IX:        9
GSR:            1
IB:             3
IFS1P3DX:       1
INV:            25
OB:             12
OR2:            8
ORCALUT4:       199
PFUMX:          4
PUR:            1
ROM16X1A:       30
VHI:            33
VLO:            33
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 34MB peak: 161MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Aug  8 18:40:17 2019

###########################################################]