| Project Settings |
|---|
| Project Name | impl1_syn | Device Name | impl1: Lattice MachXO2 : LCMXO2_7000HC |
| Implementation Name | impl1 | Top Module | FleaFPGA_Uno_E1 |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
42 |
46 |
0 |
- |
00m:01s |
- |
8/08/2019
6:40:10 PM |
| (premap) | Complete |
3 |
9 |
0 |
0m:00s |
0m:00s |
143MB |
8/08/2019
6:40:12 PM |
| (fpga_mapper) | Complete |
23 |
8 |
0 |
0m:03s |
0m:04s |
161MB |
8/08/2019
6:40:17 PM |
| Area Summary |
|---|
|
| Register bits | 179 |
I/O cells | 15 |
| Block RAMs
(v_ram) | 9 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 199 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| FleaFPGA_Uno_E1|sys_clock | 159.6 MHz | 135.7 MHz | -1.106 |
| dm7400_1|y1_inferred_clock | 164.6 MHz | 168.4 MHz | 0.136 |
| dm7400_1|y3_inferred_clock | 314.4 MHz | 267.3 MHz | -0.561 |
| dm7427|y1_inferred_clock | 292.6 MHz | 249.0 MHz | -0.598 |
| System | 160.7 MHz | 152.1 MHz | -0.354 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 4 |
| |
|