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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.10.2.115
Mon Aug 05 08:54:32 2019
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: FleaFPGA_Uno_E1
Device,speed: LCMXO2-7000HC,4
Report level: verbose report, limited to 10 items per preference
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Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
10 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 3.827ns (weighted slack = 7.654ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port apple_module/CursorBuffer/sram_1_0_0_0(ASIC) (from apple_module/mem0 -)
Destination: FF Data in apple_module/C13/states[3] (to circuit_clk +)
Delay: 6.723ns (74.1% logic, 25.9% route), 1 logic levels.
Constraint Details:
6.723ns physical path delay apple_module/CursorBuffer/sram_1_0_0_0 to apple_module/SLICE_47 meets
20.000ns delay constraint less
9.102ns skew and
0.000ns feedback compensation and
0.348ns M_SET requirement (totaling 10.550ns) by 3.827ns
Physical Path Details:
Data path apple_module/CursorBuffer/sram_1_0_0_0 to apple_module/SLICE_47:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.979 EBR_R20C10.CLKA to EBR_R20C10.DOA0 apple_module/CursorBuffer/sram_1_0_0_0 (from apple_module/mem0)
ROUTE 1 1.744 EBR_R20C10.DOA0 to R14C14B.M1 apple_module/mem_curs_out[0] (to circuit_clk)
--------
6.723 (74.1% logic, 25.9% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to apple_module/CursorBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 2.367 R14C19C.F1 to R2C19C.B0 apple_module/line_clock
CTOF_DEL --- 0.495 R2C19C.B0 to R2C19C.F0 apple_module/SLICE_64
ROUTE 14 3.980 R2C19C.F0 to EBR_R20C10.CLKA apple_module/mem0
--------
12.922 (19.9% logic, 80.1% route), 5 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/SLICE_47:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R14C14B.CLK circuit_clk
--------
3.820 (29.6% logic, 70.4% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 8.325ns (weighted slack = 16.650ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (from apple_module/line_clock -)
Destination: DP8KC Port apple_module/D2/CharacterRom_0_0_0_0(ASIC) (to circuit_clk +)
Delay: 7.843ns (63.5% logic, 36.5% route), 1 logic levels.
Constraint Details:
7.843ns physical path delay apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0 meets
20.000ns delay constraint less
3.858ns skew and
0.000ns feedback compensation and
-0.026ns ADDR_SET requirement (totaling 16.168ns) by 8.325ns
Physical Path Details:
Data path apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.979 EBR_R13C13.CLKA to EBR_R13C13.DOA3 apple_module/C3/LineBuffer/sram_1_0_0_0 (from apple_module/line_clock)
ROUTE 2 2.864 EBR_R13C13.DOA3 to EBR_R13C16.ADA9 apple_module/screen_char[3] (to circuit_clk)
--------
7.843 (63.5% logic, 36.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 1.771 R14C19C.F1 to EBR_R13C13.CLKA apple_module/line_clock
--------
7.851 (26.5% logic, 73.5% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 2.071 RPLL.CLKOS to EBR_R13C16.CLKA circuit_clk
--------
3.993 (28.3% logic, 71.7% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 8.941ns (weighted slack = 17.882ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/C7/states[1] (from apple_module/mem0 -)
Destination: FF Data in apple_module/C13/states[2] (to circuit_clk +)
Delay: 1.964ns (48.2% logic, 51.8% route), 2 logic levels.
Constraint Details:
1.964ns physical path delay apple_module/SLICE_28 to apple_module/SLICE_47 meets
20.000ns delay constraint less
8.929ns skew and
0.000ns feedback compensation and
0.166ns DIN_SET requirement (totaling 10.905ns) by 8.941ns
Physical Path Details:
Data path apple_module/SLICE_28 to apple_module/SLICE_47:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R14C12C.CLK to R14C12C.Q0 apple_module/SLICE_28 (from apple_module/mem0)
ROUTE 9 1.017 R14C12C.Q0 to R14C14B.A0 apple_module/char_ready
CTOF_DEL --- 0.495 R14C14B.A0 to R14C14B.F0 apple_module/SLICE_47
ROUTE 1 0.000 R14C14B.F0 to R14C14B.DI0 apple_module/line_curs (to circuit_clk)
--------
1.964 (48.2% logic, 51.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to apple_module/SLICE_28:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 2.367 R14C19C.F1 to R2C19C.B0 apple_module/line_clock
CTOF_DEL --- 0.495 R2C19C.B0 to R2C19C.F0 apple_module/SLICE_64
ROUTE 14 3.807 R2C19C.F0 to R14C12C.CLK apple_module/mem0
--------
12.749 (20.2% logic, 79.8% route), 5 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/SLICE_47:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R14C14B.CLK circuit_clk
--------
3.820 (29.6% logic, 70.4% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.356ns (weighted slack = 18.712ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (from apple_module/line_clock -)
Destination: DP8KC Port apple_module/D2/CharacterRom_0_0_0_0(ASIC) (to circuit_clk +)
Delay: 6.812ns (73.1% logic, 26.9% route), 1 logic levels.
Constraint Details:
6.812ns physical path delay apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0 meets
20.000ns delay constraint less
3.858ns skew and
0.000ns feedback compensation and
-0.026ns ADDR_SET requirement (totaling 16.168ns) by 9.356ns
Physical Path Details:
Data path apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.979 EBR_R13C13.CLKA to EBR_R13C13.DOA2 apple_module/C3/LineBuffer/sram_1_0_0_0 (from apple_module/line_clock)
ROUTE 2 1.833 EBR_R13C13.DOA2 to EBR_R13C16.ADA8 apple_module/screen_char[2] (to circuit_clk)
--------
6.812 (73.1% logic, 26.9% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 1.771 R14C19C.F1 to EBR_R13C13.CLKA apple_module/line_clock
--------
7.851 (26.5% logic, 73.5% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 2.071 RPLL.CLKOS to EBR_R13C16.CLKA circuit_clk
--------
3.993 (28.3% logic, 71.7% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.356ns (weighted slack = 18.712ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (from apple_module/line_clock -)
Destination: DP8KC Port apple_module/D2/CharacterRom_0_0_0_0(ASIC) (to circuit_clk +)
Delay: 6.812ns (73.1% logic, 26.9% route), 1 logic levels.
Constraint Details:
6.812ns physical path delay apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0 meets
20.000ns delay constraint less
3.858ns skew and
0.000ns feedback compensation and
-0.026ns ADDR_SET requirement (totaling 16.168ns) by 9.356ns
Physical Path Details:
Data path apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.979 EBR_R13C13.CLKA to EBR_R13C13.DOA0 apple_module/C3/LineBuffer/sram_1_0_0_0 (from apple_module/line_clock)
ROUTE 2 1.833 EBR_R13C13.DOA0 to EBR_R13C16.ADA6 apple_module/screen_char[0] (to circuit_clk)
--------
6.812 (73.1% logic, 26.9% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 1.771 R14C19C.F1 to EBR_R13C13.CLKA apple_module/line_clock
--------
7.851 (26.5% logic, 73.5% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 2.071 RPLL.CLKOS to EBR_R13C16.CLKA circuit_clk
--------
3.993 (28.3% logic, 71.7% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.433ns (weighted slack = 18.866ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (from apple_module/line_clock -)
Destination: DP8KC Port apple_module/D2/CharacterRom_0_0_0_0(ASIC) (to circuit_clk +)
Delay: 6.735ns (73.9% logic, 26.1% route), 1 logic levels.
Constraint Details:
6.735ns physical path delay apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0 meets
20.000ns delay constraint less
3.858ns skew and
0.000ns feedback compensation and
-0.026ns ADDR_SET requirement (totaling 16.168ns) by 9.433ns
Physical Path Details:
Data path apple_module/C3/LineBuffer/sram_1_0_0_0 to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.979 EBR_R13C13.CLKA to EBR_R13C13.DOA1 apple_module/C3/LineBuffer/sram_1_0_0_0 (from apple_module/line_clock)
ROUTE 2 1.756 EBR_R13C13.DOA1 to EBR_R13C16.ADA7 apple_module/screen_char[1] (to circuit_clk)
--------
6.735 (73.9% logic, 26.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 1.771 R14C19C.F1 to EBR_R13C13.CLKA apple_module/line_clock
--------
7.851 (26.5% logic, 73.5% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/D2/CharacterRom_0_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 2.071 RPLL.CLKOS to EBR_R13C16.CLKA circuit_clk
--------
3.993 (28.3% logic, 71.7% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.474ns (weighted slack = 18.948ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/da (from apple_module/un1_rda_1 +)
Destination: FF Data in apple_module/char_num[29] (to apple_module/y2_1 -)
FF apple_module/char_num[28]
Delay: 2.745ns (34.5% logic, 65.5% route), 2 logic levels.
Constraint Details:
2.745ns physical path delay SLICE_36 to apple_module/SLICE_27 meets
20.000ns delay constraint less
7.474ns skew and
0.000ns feedback compensation and
0.307ns CE_SET requirement (totaling 12.219ns) by 9.474ns
Physical Path Details:
Data path SLICE_36 to apple_module/SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R15C16D.CLK to R15C16D.Q0 SLICE_36 (from apple_module/un1_rda_1)
ROUTE 3 0.669 R15C16D.Q0 to R15C16D.A0 apple_module/da
CTOF_DEL --- 0.495 R15C16D.A0 to R15C16D.F0 SLICE_36
ROUTE 6 1.129 R15C16D.F0 to R15C15C.CE apple_module/rd20 (to apple_module/y2_1)
--------
2.745 (34.5% logic, 65.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to SLICE_36:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 2.367 R14C19C.F1 to R2C19C.B0 apple_module/line_clock
CTOF_DEL --- 0.495 R2C19C.B0 to R2C19C.F0 apple_module/SLICE_64
ROUTE 14 3.807 R2C19C.F0 to R14C14C.CLK apple_module/mem0
REG_DEL --- 0.452 R14C14C.CLK to R14C14C.Q0 apple_module/SLICE_46
ROUTE 2 1.420 R14C14C.Q0 to R14C18B.A1 apple_module/rda
CTOF_DEL --- 0.495 R14C18B.A1 to R14C18B.F1 apple_module/SLICE_68
ROUTE 1 1.056 R14C18B.F1 to R15C16D.CLK apple_module/un1_rda_1
--------
16.172 (21.8% logic, 78.2% route), 7 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/SLICE_27:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18B.CLK circuit_clk
REG_DEL --- 0.452 R15C18B.CLK to R15C18B.Q0 apple_module/D7/SLICE_42
ROUTE 11 0.715 R15C18B.Q0 to R14C18C.D1 apple_module/horz_count_upper[3]
CTOF_DEL --- 0.495 R14C18C.D1 to R14C18C.F1 apple_module/D1/SLICE_52
ROUTE 16 3.216 R14C18C.F1 to R15C15C.CLK apple_module/y2_1
--------
8.698 (23.9% logic, 76.1% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.474ns (weighted slack = 18.948ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/da (from apple_module/un1_rda_1 +)
Destination: FF Data in apple_module/rd[2] (to apple_module/y2_1 -)
FF apple_module/rd[1]
Delay: 2.745ns (34.5% logic, 65.5% route), 2 logic levels.
Constraint Details:
2.745ns physical path delay SLICE_36 to apple_module/SLICE_43 meets
20.000ns delay constraint less
7.474ns skew and
0.000ns feedback compensation and
0.307ns CE_SET requirement (totaling 12.219ns) by 9.474ns
Physical Path Details:
Data path SLICE_36 to apple_module/SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R15C16D.CLK to R15C16D.Q0 SLICE_36 (from apple_module/un1_rda_1)
ROUTE 3 0.669 R15C16D.Q0 to R15C16D.A0 apple_module/da
CTOF_DEL --- 0.495 R15C16D.A0 to R15C16D.F0 SLICE_36
ROUTE 6 1.129 R15C16D.F0 to R15C15A.CE apple_module/rd20 (to apple_module/y2_1)
--------
2.745 (34.5% logic, 65.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to SLICE_36:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 2.367 R14C19C.F1 to R2C19C.B0 apple_module/line_clock
CTOF_DEL --- 0.495 R2C19C.B0 to R2C19C.F0 apple_module/SLICE_64
ROUTE 14 3.807 R2C19C.F0 to R14C14C.CLK apple_module/mem0
REG_DEL --- 0.452 R14C14C.CLK to R14C14C.Q0 apple_module/SLICE_46
ROUTE 2 1.420 R14C14C.Q0 to R14C18B.A1 apple_module/rda
CTOF_DEL --- 0.495 R14C18B.A1 to R14C18B.F1 apple_module/SLICE_68
ROUTE 1 1.056 R14C18B.F1 to R15C16D.CLK apple_module/un1_rda_1
--------
16.172 (21.8% logic, 78.2% route), 7 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/SLICE_43:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18B.CLK circuit_clk
REG_DEL --- 0.452 R15C18B.CLK to R15C18B.Q0 apple_module/D7/SLICE_42
ROUTE 11 0.715 R15C18B.Q0 to R14C18C.D1 apple_module/horz_count_upper[3]
CTOF_DEL --- 0.495 R14C18C.D1 to R14C18C.F1 apple_module/D1/SLICE_52
ROUTE 16 3.216 R14C18C.F1 to R15C15A.CLK apple_module/y2_1
--------
8.698 (23.9% logic, 76.1% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.474ns (weighted slack = 18.948ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/da (from apple_module/un1_rda_1 +)
Destination: FF Data in apple_module/rd[4] (to apple_module/y2_1 -)
FF apple_module/rd[3]
Delay: 2.745ns (34.5% logic, 65.5% route), 2 logic levels.
Constraint Details:
2.745ns physical path delay SLICE_36 to apple_module/SLICE_44 meets
20.000ns delay constraint less
7.474ns skew and
0.000ns feedback compensation and
0.307ns CE_SET requirement (totaling 12.219ns) by 9.474ns
Physical Path Details:
Data path SLICE_36 to apple_module/SLICE_44:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R15C16D.CLK to R15C16D.Q0 SLICE_36 (from apple_module/un1_rda_1)
ROUTE 3 0.669 R15C16D.Q0 to R15C16D.A0 apple_module/da
CTOF_DEL --- 0.495 R15C16D.A0 to R15C16D.F0 SLICE_36
ROUTE 6 1.129 R15C16D.F0 to R15C15D.CE apple_module/rd20 (to apple_module/y2_1)
--------
2.745 (34.5% logic, 65.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to SLICE_36:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 2.367 R14C19C.F1 to R2C19C.B0 apple_module/line_clock
CTOF_DEL --- 0.495 R2C19C.B0 to R2C19C.F0 apple_module/SLICE_64
ROUTE 14 3.807 R2C19C.F0 to R14C14C.CLK apple_module/mem0
REG_DEL --- 0.452 R14C14C.CLK to R14C14C.Q0 apple_module/SLICE_46
ROUTE 2 1.420 R14C14C.Q0 to R14C18B.A1 apple_module/rda
CTOF_DEL --- 0.495 R14C18B.A1 to R14C18B.F1 apple_module/SLICE_68
ROUTE 1 1.056 R14C18B.F1 to R15C16D.CLK apple_module/un1_rda_1
--------
16.172 (21.8% logic, 78.2% route), 7 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/SLICE_44:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18B.CLK circuit_clk
REG_DEL --- 0.452 R15C18B.CLK to R15C18B.Q0 apple_module/D7/SLICE_42
ROUTE 11 0.715 R15C18B.Q0 to R14C18C.D1 apple_module/horz_count_upper[3]
CTOF_DEL --- 0.495 R14C18C.D1 to R14C18C.F1 apple_module/D1/SLICE_52
ROUTE 16 3.216 R14C18C.F1 to R15C15D.CLK apple_module/y2_1
--------
8.698 (23.9% logic, 76.1% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Passed: The following path meets requirements by 9.474ns (weighted slack = 18.948ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/da (from apple_module/un1_rda_1 +)
Destination: FF Data in apple_module/rd[7] (to apple_module/y2_1 -)
FF apple_module/rd[5]
Delay: 2.745ns (34.5% logic, 65.5% route), 2 logic levels.
Constraint Details:
2.745ns physical path delay SLICE_36 to apple_module/SLICE_45 meets
20.000ns delay constraint less
7.474ns skew and
0.000ns feedback compensation and
0.307ns CE_SET requirement (totaling 12.219ns) by 9.474ns
Physical Path Details:
Data path SLICE_36 to apple_module/SLICE_45:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R15C16D.CLK to R15C16D.Q0 SLICE_36 (from apple_module/un1_rda_1)
ROUTE 3 0.669 R15C16D.Q0 to R15C16D.A0 apple_module/da
CTOF_DEL --- 0.495 R15C16D.A0 to R15C16D.F0 SLICE_36
ROUTE 6 1.129 R15C16D.F0 to R15C15B.CE apple_module/rd20 (to apple_module/y2_1)
--------
2.745 (34.5% logic, 65.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clock to SLICE_36:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18D.CLK circuit_clk
REG_DEL --- 0.452 R15C18D.CLK to R15C18D.Q1 apple_module/D7/SLICE_41
ROUTE 7 1.313 R15C18D.Q1 to R14C19C.A1 apple_module/horz_count_upper[2]
CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 apple_module/SLICE_26
ROUTE 5 2.367 R14C19C.F1 to R2C19C.B0 apple_module/line_clock
CTOF_DEL --- 0.495 R2C19C.B0 to R2C19C.F0 apple_module/SLICE_64
ROUTE 14 3.807 R2C19C.F0 to R14C14C.CLK apple_module/mem0
REG_DEL --- 0.452 R14C14C.CLK to R14C14C.Q0 apple_module/SLICE_46
ROUTE 2 1.420 R14C14C.Q0 to R14C18B.A1 apple_module/rda
CTOF_DEL --- 0.495 R14C18B.A1 to R14C18B.F1 apple_module/SLICE_68
ROUTE 1 1.056 R14C18B.F1 to R15C16D.CLK apple_module/un1_rda_1
--------
16.172 (21.8% logic, 78.2% route), 7 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Destination Clock Path sys_clock to apple_module/SLICE_45:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
ROUTE 1 0.790 126.PADDI to RPLL.CLKI sys_clock_c
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
ROUTE 26 1.898 RPLL.CLKOS to R15C18B.CLK circuit_clk
REG_DEL --- 0.452 R15C18B.CLK to R15C18B.Q0 apple_module/D7/SLICE_42
ROUTE 11 0.715 R15C18B.Q0 to R14C18C.D1 apple_module/horz_count_upper[3]
CTOF_DEL --- 0.495 R14C18C.D1 to R14C18C.F1 apple_module/D1/SLICE_52
ROUTE 16 3.216 R14C18C.F1 to R15C15B.CLK apple_module/y2_1
--------
8.698 (23.9% logic, 76.1% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
Report: 30.916MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "sys_clock" 25.000000 | | |
MHz ; | 25.000 MHz| 30.916 MHz| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: apple_module/y2_1 Source: apple_module/D1/SLICE_52.F1 Loads: 16
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
Data transfers from:
Clock Domain: apple_module/line_clock Source: apple_module/SLICE_26.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
Clock Domain: apple_module/mem0 Source: apple_module/SLICE_64.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 3
Clock Domain: apple_module/mem0 Source: apple_module/SLICE_64.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 6
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: apple_module/y2_1 Source: apple_module/D1/SLICE_52.F1 Loads: 16
No transfer within this clock domain is found
Data transfers from:
Clock Domain: apple_module/un1_rda_1 Source: apple_module/SLICE_68.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/un1_rda_1 Source: apple_module/SLICE_68.F1 Loads: 1
No transfer within this clock domain is found
Data transfers from:
Clock Domain: apple_module/y2_1 Source: apple_module/D1/SLICE_52.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
Clock Domain: apple_module/y2_1 Source: apple_module/D1/SLICE_52.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
Clock Domain: apple_module/y2_1 Source: apple_module/D1/SLICE_52.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
Clock Domain: apple_module/un1_rda_1 Source: apple_module/SLICE_68.F1 Loads: 1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
Data transfers from:
Clock Domain: apple_module/y2_1 Source: apple_module/D1/SLICE_52.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 26
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
Data transfers from:
Clock Domain: apple_module/mem0 Source: apple_module/SLICE_64.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/line_clock Source: apple_module/SLICE_26.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 6
Clock Domain: apple_module/mem0 Source: apple_module/SLICE_64.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 1
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 786 paths, 10 nets, and 594 connections (98.84% coverage)