SCUBA, Version Diamond (64-bit) 3.10.2.115
Thu Aug 08 18:20:27 2019

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n sig2504 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 1 -depth 1024 -mode 8 
    Circuit name     : sig2504
    Module type      : shiftreg
    Module Version   : 5.2
    Ports            : 
	Inputs       : Din[0:0], Clock, ClockEn, Reset
	Outputs      : Q[0:0]
    I/O buffer       : not inserted
    EDIF output      : sig2504.edn
    VHDL output      : sig2504.vhd
    VHDL template    : sig2504_tmpl.vhd
    VHDL testbench    : tb_sig2504_tmpl.vhd
    VHDL purpose     : for synthesis and simulation
    Bus notation     : big endian
    Report output    : sig2504.srp
    Element Usage    :
            CU2 : 5
         FADD2B : 1
        FD1P3IX : 10
            INV : 2
            OR2 : 1
       ROM16X1A : 4
          DP8KC : 1
    Estimated Resource Usage:
            LUT : 17
            EBR : 1
            Reg : 10