-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
-- Module  Version: 5.2
-- Thu Aug 08 18:20:27 2019

-- parameterized module component declaration
component sig2504
    port (Din: in  std_logic_vector(0 downto 0); Clock: in  std_logic; 
        ClockEn: in  std_logic; Reset: in  std_logic; 
        Q: out  std_logic_vector(0 downto 0));
end component;

-- parameterized module component instance
__ : sig2504
    port map (Din(0 downto 0)=>__, Clock=>__, ClockEn=>__, Reset=>__, Q(0 downto 0)=>__);