# messages

id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: MT246
link: "c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12
kind: warning
message:
Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


id: MT420
kind: warning
message:
Found inferred clock apple1display|line_clock_inferred_clock with period 6.07ns. Please declare a user-defined clock on object "n:apple_module.line_clock"


id: MT420
kind: warning
message:
Found inferred clock apple1display|mem0_inferred_clock with period 3.71ns. Please declare a user-defined clock on object "n:apple_module.mem0"


id: MT420
kind: warning
message:
Found inferred clock dm7400|y2_1_inferred_clock with period 3.76ns. Please declare a user-defined clock on object "n:apple_module.D10.y2_1"


id: MT320
kind: note
message:
This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.


