129 lines
5.0 KiB
XML
129 lines
5.0 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="Apple1Display" device="LCMXO2-7000HC-4TG144C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="CursorRam" top="FleaFPGA_Uno_E1"/>
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<Source name="impl1/source/FleaFPGA_Uno_Top.vhd" type="VHDL" type_short="VHDL" syn_sim="SynOnly">
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<Options top_module="FleaFPGA_Uno_E1"/>
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</Source>
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<Source name="impl1/Apple1Display.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="impl1/source/ntsc.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="impl1/divider.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="impl1/master_clk.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="ttl/dm7400.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7402.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7404.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7408.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7410.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7427.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7432.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm7450.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm74157.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm74160.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm74161.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm74166.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm74174.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm74175.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/2504.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/2519.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/dm2513.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="CharacterRom.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="ScreenRom.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="ShiftReg40.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="tests/Apple1Display_tb.vhd" type="VHDL" type_short="VHDL" syn_sim="SimOnly">
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<Options/>
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</Source>
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<Source name="tests/ShiftReg40_tb.vhd" type="VHDL" type_short="VHDL" syn_sim="SimOnly">
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<Options/>
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</Source>
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<Source name="test_entity.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ShiftReg1024.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="ScreenRom2.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="ScreenRam.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="CursorRam.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="UART_RX.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="ttl/ne555.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="sig2504.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="sig2513.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="impl1/source/FleaFPGA_Uno_Top.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="simulation/simulation.spf" type="Simulation Project File" type_short="SPF">
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<Options/>
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</Source>
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<Source name="test_entity.pcf" type="Power Calculator" type_short="PCF">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="Apple1Display1.sty"/>
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</BaliProject>
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