15 lines
539 B
VHDL
15 lines
539 B
VHDL
-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
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-- Module Version: 5.2
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-- Mon Aug 05 13:43:24 2019
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-- parameterized module component declaration
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component ShiftReg1024
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port (Din: in std_logic_vector(5 downto 0); Clock: in std_logic;
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ClockEn: in std_logic; Reset: in std_logic;
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Q: out std_logic_vector(5 downto 0));
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end component;
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-- parameterized module component instance
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__ : ShiftReg1024
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port map (Din(5 downto 0)=>__, Clock=>__, ClockEn=>__, Reset=>__, Q(5 downto 0)=>__);
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