38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
SCUBA, Version Diamond (64-bit) 3.10.2.115
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Mon Aug 05 13:43:30 2019
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Issued command : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n ShiftReg40 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 6 -depth 40 -mode 8 -memfile c:/dev/apple1display/docs/lut_2519.mem -memformat bin
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Circuit name : ShiftReg40
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Module type : shiftreg
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Module Version : 5.2
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Ports :
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Inputs : Din[5:0], Clock, ClockEn, Reset
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Outputs : Q[5:0]
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I/O buffer : not inserted
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Memory file : c:/dev/apple1display/docs/lut_2519.mem
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EDIF output : ShiftReg40.edn
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VHDL output : ShiftReg40.vhd
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VHDL template : ShiftReg40_tmpl.vhd
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VHDL testbench : tb_ShiftReg40_tmpl.vhd
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VHDL purpose : for synthesis and simulation
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Bus notation : big endian
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Report output : ShiftReg40.srp
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Element Usage :
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CU2 : 3
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FADD2B : 1
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FD1P3IX : 6
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INV : 4
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OR2 : 1
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ROM16X1A : 2
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DP8KC : 1
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Estimated Resource Usage:
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LUT : 11
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EBR : 1
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Reg : 6
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