142 lines
4.1 KiB
VHDL
142 lines
4.1 KiB
VHDL
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-- File Downloaded from http://www.nandland.com
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----------------------------------------------------------------------
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-- This file contains the UART Receiver. This receiver is able to
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-- receive 8 bits of serial data, one start bit, one stop bit,
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-- and no parity bit. When receive is complete o_rx_dv will be
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-- driven high for one clock cycle.
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--
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-- Set Generic g_CLKS_PER_BIT as follows:
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-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
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-- Example: 10 MHz Clock, 115200 baud UART
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-- (10000000)/(115200) = 87
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--
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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entity UART_RX is
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generic (
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g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
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);
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port (
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i_Clk : in std_logic;
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i_RX_Serial : in std_logic;
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o_RX_DV : out std_logic;
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o_RX_Byte : out std_logic_vector(7 downto 0)
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);
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end UART_RX;
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architecture rtl of UART_RX is
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type t_SM_Main is (s_Idle, s_RX_Start_Bit, s_RX_Data_Bits,
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s_RX_Stop_Bit, s_Cleanup);
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signal r_SM_Main : t_SM_Main := s_Idle;
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signal r_RX_Data_R : std_logic := '0';
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signal r_RX_Data : std_logic := '0';
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signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
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signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
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signal r_RX_Byte : std_logic_vector(7 downto 0) := (others => '0');
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signal r_RX_DV : std_logic := '0';
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begin
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-- Purpose: Double-register the incoming data.
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-- This allows it to be used in the UART RX Clock Domain.
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-- (It removes problems caused by metastabiliy)
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p_SAMPLE : process (i_Clk)
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begin
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if rising_edge(i_Clk) then
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r_RX_Data_R <= i_RX_Serial;
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r_RX_Data <= r_RX_Data_R;
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end if;
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end process p_SAMPLE;
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-- Purpose: Control RX state machine
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p_UART_RX : process (i_Clk)
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begin
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if rising_edge(i_Clk) then
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case r_SM_Main is
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when s_Idle =>
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r_RX_DV <= '0';
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r_Clk_Count <= 0;
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r_Bit_Index <= 0;
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if r_RX_Data = '0' then -- Start bit detected
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r_SM_Main <= s_RX_Start_Bit;
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else
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r_SM_Main <= s_Idle;
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end if;
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-- Check middle of start bit to make sure it's still low
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when s_RX_Start_Bit =>
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if r_Clk_Count = (g_CLKS_PER_BIT-1)/2 then
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if r_RX_Data = '0' then
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r_Clk_Count <= 0; -- reset counter since we found the middle
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r_SM_Main <= s_RX_Data_Bits;
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else
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r_SM_Main <= s_Idle;
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end if;
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else
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r_Clk_Count <= r_Clk_Count + 1;
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r_SM_Main <= s_RX_Start_Bit;
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end if;
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-- Wait g_CLKS_PER_BIT-1 clock cycles to sample serial data
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when s_RX_Data_Bits =>
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if r_Clk_Count < g_CLKS_PER_BIT-1 then
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r_Clk_Count <= r_Clk_Count + 1;
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r_SM_Main <= s_RX_Data_Bits;
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else
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r_Clk_Count <= 0;
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r_RX_Byte(r_Bit_Index) <= r_RX_Data;
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-- Check if we have sent out all bits
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if r_Bit_Index < 7 then
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r_Bit_Index <= r_Bit_Index + 1;
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r_SM_Main <= s_RX_Data_Bits;
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else
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r_Bit_Index <= 0;
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r_SM_Main <= s_RX_Stop_Bit;
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end if;
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end if;
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-- Receive Stop bit. Stop bit = 1
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when s_RX_Stop_Bit =>
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-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
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if r_Clk_Count < g_CLKS_PER_BIT-1 then
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r_Clk_Count <= r_Clk_Count + 1;
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r_SM_Main <= s_RX_Stop_Bit;
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else
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r_RX_DV <= '1';
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r_Clk_Count <= 0;
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r_SM_Main <= s_Cleanup;
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end if;
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-- Stay here 1 clock
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when s_Cleanup =>
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r_SM_Main <= s_Idle;
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r_RX_DV <= '0';
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when others =>
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r_SM_Main <= s_Idle;
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end case;
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end if;
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end process p_UART_RX;
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o_RX_DV <= r_RX_DV;
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o_RX_Byte <= r_RX_Byte;
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end rtl; |