277 lines
12 KiB
Plaintext
277 lines
12 KiB
Plaintext
PAR: Place And Route Diamond (64-bit) 3.10.2.115.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Thu Aug 08 18:39:21 2019
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C:/lscc/diamond/3.10_x64/ispfpga\bin\nt64\par -f Apple1Display_impl1.p2t
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Apple1Display_impl1_map.ncd Apple1Display_impl1.dir Apple1Display_impl1.prf
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-gui -msgset C:/Dev/Apple1Display/promote.xml
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Preference file: Apple1Display_impl1.prf.
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 -67.249 8347443 -3.228 79282 17 Success
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* : Design saved.
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Total (real) run time for 1-seed: 17 secs
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par done!
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Lattice Place and Route Report for Design "Apple1Display_impl1_map.ncd"
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Thu Aug 08 18:39:21 2019
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PAR: Place And Route Diamond (64-bit) 3.10.2.115.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Dev/Apple1Display/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF Apple1Display_impl1_map.ncd Apple1Display_impl1.dir/5_1.ncd Apple1Display_impl1.prf
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Preference file: Apple1Display_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file Apple1Display_impl1_map.ncd.
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Design name: FleaFPGA_Uno_E1
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-7000HC
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Package: TQFP144
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Performance: 4
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Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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License checked out.
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Ignore Preference Error(s): True
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Device utilization summary:
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PIO (prelim) 15+4(JTAG)/336 6% used
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15+4(JTAG)/115 17% bonded
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IOLOGIC 1/336 <1% used
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SLICE 153/3432 4% used
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GSR 1/1 100% used
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EBR 9/26 34% used
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PLL 1/2 50% used
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INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
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INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
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Number of Signals: 528
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Number of Connections: 1242
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Pin Constraint Summary:
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13 out of 15 pins locked (86% locked).
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WARNING - par: RPLL must be put in reset state during background Flash programming. System design must take this into consideration when PLL is used during background Flash programming. Please see TN1204 MachXO2 Programming and Configuration Usage Guide for detailed information.
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The following 3 signals are selected to use the primary clock routing resources:
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circuit_clk (driver: clock_module/PLLInst_0, clk load #: 24)
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apple_module/C5/y1 (driver: apple_module/SLICE_127, clk load #: 47)
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sys_clock_c (driver: sys_clock, clk load #: 38)
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The following 1 signal is selected to use the secondary clock routing resources:
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un1_flash_countlt22 (driver: SLICE_122, clk load #: 0, sr load #: 4, ce load #: 11)
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Signal apple_module/horz_count_upper[3] is selected as Global Set/Reset.
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.
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Starting Placer Phase 0.
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............
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Finished Placer Phase 0. REAL time: 2 secs
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Starting Placer Phase 1.
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...................
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Placer score = 67613.
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Finished Placer Phase 1. REAL time: 8 secs
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Starting Placer Phase 2.
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.
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Placer score = 67327
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Finished Placer Phase 2. REAL time: 8 secs
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------------------ Clock Report ------------------
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Global Clock Resources:
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CLK_PIN : 1 out of 8 (12%)
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PLL : 1 out of 2 (50%)
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DCM : 0 out of 2 (0%)
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DCC : 0 out of 8 (0%)
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Quadrants All (TL, TR, BL, BR) - Global Clocks:
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PRIMARY "circuit_clk" from CLKOS on comp "clock_module/PLLInst_0" on PLL site "RPLL", clk load = 24
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PRIMARY "apple_module/C5/y1" from F0 on comp "apple_module/SLICE_127" on site "R2C19D", clk load = 47
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PRIMARY "sys_clock_c" from comp "sys_clock" on CLK_PIN site "126 (PT22C)", clk load = 38
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SECONDARY "un1_flash_countlt22" from F1 on comp "SLICE_122" on site "R21C21B", clk load = 0, ce load = 11, sr load = 4
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PRIMARY : 3 out of 8 (37%)
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SECONDARY: 1 out of 8 (12%)
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Edge Clocks:
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No edge clock selected.
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--------------- End of Clock Report ---------------
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I/O Usage Summary (final):
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15 + 4(JTAG) out of 336 (5.7%) PIO sites used.
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15 + 4(JTAG) out of 115 (16.5%) bonded PIO sites used.
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Number of PIO comps: 15; differential: 0.
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Number of Vref pins used: 0.
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I/O Bank Usage Summary:
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+----------+---------------+------------+-----------+
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| I/O Bank | Usage | Bank Vccio | Bank Vref |
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+----------+---------------+------------+-----------+
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| 0 | 4 / 28 ( 14%) | 3.3V | - |
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| 1 | 2 / 29 ( 6%) | 3.3V | - |
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| 2 | 1 / 29 ( 3%) | 2.5V | - |
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| 3 | 3 / 9 ( 33%) | 3.3V | - |
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| 4 | 2 / 10 ( 20%) | 2.5V | - |
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| 5 | 3 / 10 ( 30%) | 3.3V | - |
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+----------+---------------+------------+-----------+
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Total placer CPU time: 7 secs
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Dumping design to file Apple1Display_impl1.dir/5_1.ncd.
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0 connections routed; 1242 unrouted.
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Starting router resource preassignment
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=apple_module/D10/y3 loads=4 clock_loads=4
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Signal=apple_module/D10/y1 loads=4 clock_loads=4
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Completed router resource preassignment. Real time: 10 secs
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Start NBR router at 18:39:31 08/08/19
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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in the earlier iterations. In each iteration, it tries to
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solve the conflicts while keeping the critical connections
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routed as short as possible. The routing process is said to
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be completed when no conflicts exist and all connections
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are routed.
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Note: NBR uses a different method to calculate timing slacks. The
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worst slack and total negative slack may not be the same as
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that in TRCE report. You should always run TRCE to verify
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your design.
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*****************************************************************
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Start NBR special constraint process at 18:39:31 08/08/19
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Start NBR section for initial routing at 18:39:32 08/08/19
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Level 1, iteration 1
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8(0.00%) conflicts; 853(68.68%) untouched conns; 3047471 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -64.043ns/-3047.471ns; real time: 11 secs
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Level 2, iteration 1
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3(0.00%) conflicts; 852(68.60%) untouched conns; 3049688 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -64.050ns/-3049.688ns; real time: 11 secs
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Level 3, iteration 1
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1(0.00%) conflict; 852(68.60%) untouched conns; 3070265 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -64.519ns/-3070.265ns; real time: 11 secs
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Level 4, iteration 1
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15(0.00%) conflicts; 0(0.00%) untouched conn; 3111371 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -65.450ns/-3111.372ns; real time: 12 secs
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Info: Initial congestion level at 75% usage is 0
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Info: Initial congestion area at 75% usage is 0 (0.00%)
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Start NBR section for normal routing at 18:39:33 08/08/19
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Level 4, iteration 1
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13(0.00%) conflicts; 0(0.00%) untouched conn; 3090850 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -64.981ns/-3090.850ns; real time: 13 secs
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Level 4, iteration 2
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9(0.00%) conflicts; 0(0.00%) untouched conn; 3092562 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -64.981ns/-3092.562ns; real time: 13 secs
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Level 4, iteration 3
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7(0.00%) conflicts; 0(0.00%) untouched conn; 3112775 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -65.450ns/-3112.776ns; real time: 14 secs
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Level 4, iteration 4
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5(0.00%) conflicts; 0(0.00%) untouched conn; 3112775 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -65.450ns/-3112.776ns; real time: 14 secs
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Level 4, iteration 5
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2(0.00%) conflicts; 0(0.00%) untouched conn; 3200927 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3200.927ns; real time: 14 secs
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Level 4, iteration 6
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1(0.00%) conflict; 0(0.00%) untouched conn; 3200927 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3200.927ns; real time: 15 secs
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Level 4, iteration 7
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2(0.00%) conflicts; 0(0.00%) untouched conn; 3204119 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3204.119ns; real time: 15 secs
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Level 4, iteration 8
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1(0.00%) conflict; 0(0.00%) untouched conn; 3204119 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3204.119ns; real time: 15 secs
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Level 4, iteration 9
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0(0.00%) conflict; 0(0.00%) untouched conn; 3188906 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3188.906ns; real time: 15 secs
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Start NBR section for performance tuning (iteration 1) at 18:39:36 08/08/19
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 3188906 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3188.906ns; real time: 15 secs
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Start NBR section for re-routing at 18:39:36 08/08/19
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 3188906 (nbr) score;
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Estimated worst slack/total negative slack<setup>: -67.249ns/-3188.906ns; real time: 15 secs
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Start NBR section for post-routing at 18:39:36 08/08/19
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End NBR router with 0 unrouted connection
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NBR Summary
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-----------
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Number of unrouted connections : 0 (0.00%)
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Number of connections with timing violations : 59 (4.75%)
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Estimated worst slack<setup> : -67.249ns
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Timing score<setup> : 8347444
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=apple_module/D10/y3 loads=4 clock_loads=4
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Signal=apple_module/D10/y1 loads=4 clock_loads=4
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Total CPU time 15 secs
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Total REAL time: 17 secs
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Completely routed.
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End of route. 1242 routed (100.00%); 0 unrouted.
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Hold time timing score: 79, hold timing errors: 37
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Timing score: 8347443
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Dumping design to file Apple1Display_impl1.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Run status = Success
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PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Worst slack<setup/<ns>> = -67.249
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PAR_SUMMARY::Timing score<setup/<ns>> = 8347.444
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PAR_SUMMARY::Worst slack<hold /<ns>> = -3.228
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PAR_SUMMARY::Timing score<hold /<ns>> = 79.282
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PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 15 secs
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Total REAL time to completion: 17 secs
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par done!
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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