1016 lines
75 KiB
Plaintext
1016 lines
75 KiB
Plaintext
#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
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#install: C:\lscc\diamond\3.10_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: MARKF-PRO
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# Thu Aug 8 18:39:09 2019
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.10_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
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@N:"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Top entity is set to FleaFPGA_Uno_E1.
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Options changed - recompiling
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@W: CD433 :"C:\Dev\Apple1Display\ttl\2504.vhd":1:9:1:9|No design units in file
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VHDL syntax check successful!
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Options changed - recompiling
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@N: CD630 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Synthesizing work.fleafpga_uno_e1.arch.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":122:23:122:37|Port clkop of entity work.master_clk is unconnected. If a port needs to remain unconnected, use the keyword open.
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@N: CD630 :"C:\Dev\Apple1Display\UART_RX.vhd":18:7:18:13|Synthesizing work.uart_rx.rtl.
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@N: CD231 :"C:\Dev\Apple1Display\UART_RX.vhd":33:17:33:18|Using onehot encoding for type t_sm_main. For example, enumeration s_idle is mapped to "10000".
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@N: CD604 :"C:\Dev\Apple1Display\UART_RX.vhd":132:8:132:21|OTHERS clause is not synthesized.
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Post processing for work.uart_rx.rtl
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@N: CD630 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":7:7:7:19|Synthesizing work.apple1display.behavior.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":191:13:191:24|Port carry of entity work.dm74161 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":226:14:226:24|Port y2 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":226:14:226:24|Port y1 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|Port y5 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|Port y3 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|Port y2 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":241:14:241:24|Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q0_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q1_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q2_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q3_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q4_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q5_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":354:12:355:4|Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":367:13:368:4|Port y4 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":367:13:368:4|Port y1 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":374:12:375:4|Port y3 of entity work.dm7432 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":381:12:382:4|Port y3 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":381:12:382:4|Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|Port y2 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|Port y1 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:7:47:22|Signal buffer_char_in_0 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:25:47:40|Signal buffer_char_in_1 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:43:47:58|Signal buffer_char_in_2 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:61:47:76|Signal buffer_char_in_3 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:79:47:94|Signal buffer_char_in_4 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:97:47:112|Signal buffer_char_in_5 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":65:7:65:19|Signal unconnected_1 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":80:7:80:16|Signal cross_talk is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7400.vhd":6:7:6:12|Synthesizing work.dm7400.behavior.
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Post processing for work.dm7400.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7410.vhd":6:7:6:12|Synthesizing work.dm7410.behavior.
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Post processing for work.dm7410.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7432.vhd":6:7:6:12|Synthesizing work.dm7432.behavior.
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Post processing for work.dm7432.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7408.vhd":6:7:6:12|Synthesizing work.dm7408.behavior.
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Post processing for work.dm7408.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7450.vhd":6:7:6:12|Synthesizing work.dm7450.behavior.
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Post processing for work.dm7450.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7427.vhd":6:7:6:12|Synthesizing work.dm7427.behavior.
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Post processing for work.dm7427.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\ne555.vhd":7:7:7:11|Synthesizing work.ne555.behavior.
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Post processing for work.ne555.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74174.vhd":8:7:8:13|Synthesizing work.dm74174.behavior.
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Post processing for work.dm74174.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74157.vhd":6:7:6:13|Synthesizing work.dm74157.behavior.
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Post processing for work.dm74157.behavior
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@N: CD630 :"C:\Dev\Apple1Display\sig2504.vhd":14:7:14:13|Synthesizing work.sig2504.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1407:10:1407:17|Synthesizing work.rom16x1a.syn_black_box.
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Post processing for work.rom16x1a.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1699:10:1699:14|Synthesizing work.dp8kc.syn_black_box.
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Post processing for work.dp8kc.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":246:10:246:16|Synthesizing work.fd1p3ix.syn_black_box.
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Post processing for work.fd1p3ix.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":167:10:167:12|Synthesizing work.cu2.syn_black_box.
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Post processing for work.cu2.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":177:10:177:15|Synthesizing work.fadd2b.syn_black_box.
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Post processing for work.fadd2b.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1483:10:1483:12|Synthesizing work.vhi.syn_black_box.
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Post processing for work.vhi.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1490:10:1490:12|Synthesizing work.vlo.syn_black_box.
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Post processing for work.vlo.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":681:10:681:12|Synthesizing work.inv.syn_black_box.
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Post processing for work.inv.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1276:10:1276:12|Synthesizing work.or2.syn_black_box.
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Post processing for work.or2.syn_black_box
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Post processing for work.sig2504.structure
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@N: CD630 :"C:\Dev\Apple1Display\ttl\2519.vhd":8:7:8:13|Synthesizing work.ttl2519.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ShiftReg40.vhd":14:7:14:16|Synthesizing work.shiftreg40.structure.
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Post processing for work.shiftreg40.structure
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Post processing for work.ttl2519.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7404.vhd":6:7:6:12|Synthesizing work.dm7404.behavior.
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Post processing for work.dm7404.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7402.vhd":6:7:6:12|Synthesizing work.dm7402.behavior.
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Post processing for work.dm7402.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74166.vhd":6:7:6:13|Synthesizing work.dm74166.behavior.
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Post processing for work.dm74166.behavior
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@N: CD630 :"C:\Dev\Apple1Display\sig2513.vhd":14:7:14:13|Synthesizing work.sig2513.structure.
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Post processing for work.sig2513.structure
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74161.vhd":6:7:6:13|Synthesizing work.dm74161.behavior.
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Post processing for work.dm74161.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74160.vhd":6:7:6:13|Synthesizing work.dm74160.behavior.
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Post processing for work.dm74160.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74175.vhd":8:7:8:13|Synthesizing work.dm74175.behavior.
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Post processing for work.dm74175.behavior
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Post processing for work.apple1display.behavior
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:97:47:112|Signal buffer_char_in_5 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:79:47:94|Signal buffer_char_in_4 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:61:47:76|Signal buffer_char_in_3 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:43:47:58|Signal buffer_char_in_2 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:25:47:40|Signal buffer_char_in_1 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:7:47:22|Signal buffer_char_in_0 is floating; a simulation mismatch is possible.
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":272:15:272:26|Input din of instance D14b is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":271:15:271:26|Input din of instance D14a is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":270:14:270:25|Input din of instance D4b is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":269:14:269:25|Input din of instance D4a is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":268:14:268:25|Input din of instance D5b is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":267:14:267:25|Input din of instance D5a is floating
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@N: CD630 :"C:\Dev\Apple1Display\impl1\master_clk.vhd":14:7:14:16|Synthesizing work.master_clk.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":2221:10:2221:16|Synthesizing work.ehxpllj.syn_black_box.
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Post processing for work.ehxpllj.syn_black_box
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Post processing for work.master_clk.structure
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Post processing for work.fleafpga_uno_e1.arch
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@N: CL201 :"C:\Dev\Apple1Display\UART_RX.vhd":62:4:62:5|Trying to extract state machine for register r_SM_Main.
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Extracted state machine for register r_SM_Main
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State machine has 5 reachable states with original encodings of:
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00001
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00010
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00100
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01000
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10000
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@W: CL249 :"C:\Dev\Apple1Display\UART_RX.vhd":62:4:62:5|Initial value is not supported on state machine r_SM_Main
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@N: CL189 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":165:2:165:3|Register bit flash_count(23) is always 1.
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@W: CL260 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":165:2:165:3|Pruning register bit 23 of flash_count(23 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:10 2019
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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File C:\Dev\Apple1Display\impl1\synwork\layer0.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:10 2019
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:10 2019
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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File C:\Dev\Apple1Display\impl1\synwork\Apple1Display_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:11 2019
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###########################################################]
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Pre-mapping Report
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# Thu Aug 8 18:39:11 2019
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Dev\Apple1Display\impl1\Apple1Display_impl1_scck.rpt
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Printing clock summary report in "C:\Dev\Apple1Display\impl1\Apple1Display_impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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@W: BN287 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Register states[3:0] with reset has an initial value of 1. Ignoring initial value.
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@W: BN287 :"c:\dev\apple1display\ttl\dm74174.vhd":34:2:34:3|Register states[5:0] with reset has an initial value of 1. Ignoring initial value.
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@N: BN362 :"c:\dev\apple1display\uart_rx.vhd":62:4:62:5|Removing sequential instance r_RX_Byte[7] (in view: work.UART_RX(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
|
|
syn_allowed_resources : blockrams=26 set on top level netlist FleaFPGA_Uno_E1
|
|
|
|
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
|
|
|
|
|
|
|
Clock Summary
|
|
******************
|
|
|
|
Start Requested Requested Clock Clock Clock
|
|
Level Clock Frequency Period Type Group Load
|
|
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
0 - System 1.0 MHz 1000.000 system system_clkgroup 0
|
|
|
|
0 - dm7427|y1_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_3 83
|
|
|
|
0 - FleaFPGA_Uno_E1|sys_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 57
|
|
|
|
0 - dm7400_1|y3_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_2 44
|
|
|
|
0 - dm74175|q0_i_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_5 13
|
|
1 . dm74161_4|count_derived_clock[3] 1.0 MHz 1000.000 derived (from dm74175|q0_i_inferred_clock) Inferred_clkgroup_5 21
|
|
|
|
0 - dm7400_1|y1_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_4 7
|
|
|
|
0 - master_clk|CLKOS_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 6
|
|
=========================================================================================================================================================
|
|
|
|
@W: MT529 :"c:\dev\apple1display\uart_rx.vhd":37:36:37:38|Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
@W: MT529 :"c:\dev\apple1display\sig2504.vhd":187:4:187:15|Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.D5a.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
@W: MT529 :"c:\dev\apple1display\shiftreg40.vhd":186:4:186:15|Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
|
|
Finished Pre Mapping Phase.
|
|
|
|
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
|
|
|
Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
|
|
original code -> new code
|
|
00001 -> 000
|
|
00010 -> 001
|
|
00100 -> 010
|
|
01000 -> 011
|
|
10000 -> 100
|
|
|
|
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
|
|
|
None
|
|
None
|
|
|
|
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
|
|
|
Pre-mapping successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
|
# Thu Aug 8 18:39:12 2019
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|
|
###########################################################]
|
|
Map & Optimize Report
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|
|
# Thu Aug 8 18:39:12 2019
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|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
|
|
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
|
Product Version M-2017.03L-SP1-1
|
|
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
|
|
|
@N: MF248 |Running in 64-bit mode.
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
|
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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|
|
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|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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|
|
|
Available hyper_sources - for debug and ip models
|
|
None Found
|
|
|
|
@N: FX493 |Applying initial value "00000000" on instance uart_module.r_RX_Byte[7:0].
|
|
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
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|
|
|
@N: BN362 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Removing sequential instance flash_count[22] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74160.vhd":25:2:25:3|Found counter in view:work.apple1display(behavior) instance D6.count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_3(behavior) instance count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_2(behavior) instance count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_1(behavior) instance count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_0(behavior) instance count[3:0]
|
|
Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
|
|
original code -> new code
|
|
00001 -> 000
|
|
00010 -> 001
|
|
00100 -> 010
|
|
01000 -> 011
|
|
10000 -> 100
|
|
|
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
|
|
|
|
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
|
Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
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|
|
|
@N: BN362 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Removing sequential instance apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
|
|
@A: BN291 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Boundary register apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
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|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
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|
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|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
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|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
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|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
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|
|
|
|
|
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
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|
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Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)
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|
|
Pass CPU time Worst Slack Luts / Registers
|
|
------------------------------------------------------------
|
|
1 0h:00m:01s 990.85ns 151 / 99
|
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|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)
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|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_6_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_5_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_4_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_3_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_2_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_1_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_0_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)
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|
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@N: MT611 :|Automatically generated clock master_clk|CLKOS_inferred_clock is not used and is being removed
|
|
@N: MT611 :|Automatically generated clock dm74175|q0_i_inferred_clock is not used and is being removed
|
|
@N: MT617 :|Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 54 clock pin(s) of sequential element(s)
|
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4 gated/generated clock tree(s) driving 131 clock pin(s) of sequential element(s)
|
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0 instances converted, 131 sequential instances remain driven by gated/generated clocks
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|
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=========================== Non-Gated/Non-Generated Clocks ============================
|
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
|
---------------------------------------------------------------------------------------
|
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@K:CKID0005 sys_clock port 54 flash_count[0]
|
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=======================================================================================
|
|
===================================================================================================================== Gated/Generated Clocks ======================================================================================================================
|
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
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@K:CKID0001 clock_module.PLLInst_0 EHXPLLJ 35 apple_module.D1.Qd Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
|
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@K:CKID0002 apple_module.C5.y1 ORCALUT4 83 apple_module.C7.states[5] Multiple clocks on instance from nets line_clock, vbl_i
|
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@K:CKID0003 apple_module.D10.y1 ORCALUT4 7 apple_module.C3.LineBuffer.FF_0 No gated clock conversion method for cell cell:LUCENT.FD1P3IX
|
|
@K:CKID0004 apple_module.D10.y3_inferred_clock_RNO ORCALUT4 6 apple_module.D13.flash_counter[0] No clocks found on inputs
|
|
===================================================================================================================================================================================================================================================================
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|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
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|
|
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 147MB)
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|
|
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Writing Analyst data base C:\Dev\Apple1Display\impl1\synwork\Apple1Display_impl1_m.srm
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|
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 147MB)
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|
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Writing EDIF Netlist and constraint files
|
|
@N: FX1056 |Writing EDF file: C:\Dev\Apple1Display\impl1\Apple1Display_impl1.edi
|
|
M-2017.03L-SP1-1
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
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Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
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@W: MT246 :"c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
|
@W: MT420 |Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 1000.00ns. Please declare a user-defined clock on object "p:sys_clock"
|
|
@W: MT420 |Found inferred clock dm7427|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.C5.y1"
|
|
@W: MT420 |Found inferred clock dm7400_1|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y1"
|
|
@W: MT420 |Found inferred clock dm7400_1|y3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y3"
|
|
|
|
|
|
##### START OF TIMING REPORT #####[
|
|
# Timing Report written on Thu Aug 8 18:39:15 2019
|
|
#
|
|
|
|
|
|
Top view: FleaFPGA_Uno_E1
|
|
Requested Frequency: 1.0 MHz
|
|
Wire load mode: top
|
|
Paths requested: 5
|
|
Constraint File(s):
|
|
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
|
|
|
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
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|
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|
|
|
|
Performance Summary
|
|
*******************
|
|
|
|
|
|
Worst slack in design: 991.335
|
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
|
-----------------------------------------------------------------------------------------------------------------------------------
|
|
FleaFPGA_Uno_E1|sys_clock 1.0 MHz 115.4 MHz 1000.000 8.665 991.335 inferred Inferred_clkgroup_0
|
|
dm7400_1|y1_inferred_clock 1.0 MHz 168.4 MHz 1000.000 5.938 994.062 inferred Inferred_clkgroup_4
|
|
dm7400_1|y3_inferred_clock 1.0 MHz 262.2 MHz 1000.000 3.813 996.187 inferred Inferred_clkgroup_2
|
|
dm7427|y1_inferred_clock 1.0 MHz 218.9 MHz 1000.000 4.569 995.431 inferred Inferred_clkgroup_3
|
|
System 1.0 MHz 151.3 MHz 1000.000 6.608 993.392 system system_clkgroup
|
|
===================================================================================================================================
|
|
|
|
|
|
|
|
|
|
|
|
Clock Relationships
|
|
*******************
|
|
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------
|
|
System System | 1000.000 993.392 | No paths - | No paths - | No paths -
|
|
System dm7427|y1_inferred_clock | 1000.000 995.399 | No paths - | No paths - | No paths -
|
|
System dm7400_1|y1_inferred_clock | 1000.000 994.080 | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock System | 1000.000 991.943 | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock FleaFPGA_Uno_E1|sys_clock | 1000.000 991.335 | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock dm7427|y1_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock dm7400_1|y1_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
|
|
dm7400_1|y3_inferred_clock dm7400_1|y3_inferred_clock | No paths - | 1000.000 996.187 | No paths - | No paths -
|
|
dm7400_1|y3_inferred_clock dm7400_1|y1_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
|
|
dm7427|y1_inferred_clock System | 1000.000 993.424 | No paths - | No paths - | No paths -
|
|
dm7427|y1_inferred_clock FleaFPGA_Uno_E1|sys_clock | Diff grp - | No paths - | No paths - | No paths -
|
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dm7427|y1_inferred_clock dm7427|y1_inferred_clock | 1000.000 995.431 | No paths - | No paths - | No paths -
|
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dm7427|y1_inferred_clock dm7400_1|y1_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
|
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dm7400_1|y1_inferred_clock System | 1000.000 994.581 | No paths - | No paths - | No paths -
|
|
dm7400_1|y1_inferred_clock dm7400_1|y1_inferred_clock | 1000.000 994.062 | No paths - | No paths - | No paths -
|
|
==================================================================================================================================================
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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|
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Interface Information
|
|
*********************
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|
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No IO constraint found
|
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|
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====================================
|
|
Detailed Report for Clock: FleaFPGA_Uno_E1|sys_clock
|
|
====================================
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|
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Starting Points with Worst Slack
|
|
********************************
|
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|
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Starting Arrival
|
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
|
-----------------------------------------------------------------------------------------------------------------------
|
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uart_module.r_Clk_Count[3] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[3] 1.108 991.335
|
|
uart_module.r_Clk_Count[4] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[4] 1.108 991.335
|
|
uart_module.r_Clk_Count[5] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[5] 1.108 991.335
|
|
uart_module.r_Clk_Count[6] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[6] 1.108 991.335
|
|
uart_module.r_Clk_Count[0] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[0] 1.044 991.607
|
|
uart_module.r_Clk_Count[1] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[1] 1.044 991.607
|
|
uart_module.r_Clk_Count[2] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[2] 1.044 991.607
|
|
rd[0] FleaFPGA_Uno_E1|sys_clock FD1P3JX Q rd[0] 1.044 991.943
|
|
rd[3] FleaFPGA_Uno_E1|sys_clock FD1P3JX Q rd[3] 1.044 991.943
|
|
flash_count[2] FleaFPGA_Uno_E1|sys_clock FD1P3AX Q flash_count[2] 1.044 992.273
|
|
=======================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
----------------------------------------------------------------------------------------------------------------------------
|
|
uart_module.r_Clk_Count[5] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[5] 1000.089 991.335
|
|
uart_module.r_Clk_Count[6] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[6] 1000.089 991.335
|
|
uart_module.r_Clk_Count[3] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[3] 1000.089 991.477
|
|
uart_module.r_Clk_Count[7] FleaFPGA_Uno_E1|sys_clock FD1S3IX D un1_r_Clk_Count[0] 999.894 991.614
|
|
uart_module.r_Clk_Count[2] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[2] 1000.089 991.620
|
|
uart_module.r_Clk_Count[4] FleaFPGA_Uno_E1|sys_clock FD1S3IX D un1_r_Clk_Count[3] 999.894 991.900
|
|
uart_module.r_Clk_Count[1] FleaFPGA_Uno_E1|sys_clock FD1S3IX D un1_r_Clk_Count[6] 999.894 992.043
|
|
da FleaFPGA_Uno_E1|sys_clock FD1S3IX CD da_0_sqmuxa 999.197 992.273
|
|
rd[0] FleaFPGA_Uno_E1|sys_clock FD1P3JX SP un1_flash_count_1 999.528 992.605
|
|
rd[1] FleaFPGA_Uno_E1|sys_clock FD1P3JX SP un1_flash_count_1 999.528 992.605
|
|
============================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: -0.089
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 1000.089
|
|
|
|
- Propagation time: 8.754
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : 991.335
|
|
|
|
Number of logic level(s): 8
|
|
Starting point: uart_module.r_Clk_Count[3] / Q
|
|
Ending point: uart_module.r_Clk_Count[6] / D
|
|
The start point is clocked by FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
|
|
The end point is clocked by FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------
|
|
uart_module.r_Clk_Count[3] FD1S3IX Q Out 1.108 1.108 -
|
|
r_Clk_Count[3] Net - - - - 3
|
|
uart_module.r_SM_Main_ns_2_0_.m12 ORCALUT4 A In 0.000 1.108 -
|
|
uart_module.r_SM_Main_ns_2_0_.m12 ORCALUT4 Z Out 1.193 2.301 -
|
|
N_13 Net - - - - 4
|
|
uart_module.r_SM_Main_ns_2_0_.m13 ORCALUT4 B In 0.000 2.301 -
|
|
uart_module.r_SM_Main_ns_2_0_.m13 ORCALUT4 Z Out 1.225 3.525 -
|
|
N_14 Net - - - - 5
|
|
uart_module.un1_r_Clk_Count_2_sqmuxa ORCALUT4 C In 0.000 3.525 -
|
|
uart_module.un1_r_Clk_Count_2_sqmuxa ORCALUT4 Z Out 1.233 4.758 -
|
|
un1_r_Clk_Count_2_sqmuxa Net - - - - 6
|
|
uart_module.un1_r_Clk_Count_cry_0_0 CCU2D B0 In 0.000 4.758 -
|
|
uart_module.un1_r_Clk_Count_cry_0_0 CCU2D COUT Out 1.544 6.303 -
|
|
un1_r_Clk_Count_cry_0 Net - - - - 1
|
|
uart_module.un1_r_Clk_Count_cry_1_0 CCU2D CIN In 0.000 6.303 -
|
|
uart_module.un1_r_Clk_Count_cry_1_0 CCU2D COUT Out 0.143 6.446 -
|
|
un1_r_Clk_Count_cry_2 Net - - - - 1
|
|
uart_module.un1_r_Clk_Count_cry_3_0 CCU2D CIN In 0.000 6.446 -
|
|
uart_module.un1_r_Clk_Count_cry_3_0 CCU2D COUT Out 0.143 6.588 -
|
|
un1_r_Clk_Count_cry_4 Net - - - - 1
|
|
uart_module.un1_r_Clk_Count_cry_5_0 CCU2D CIN In 0.000 6.588 -
|
|
uart_module.un1_r_Clk_Count_cry_5_0 CCU2D S1 Out 1.549 8.137 -
|
|
un1_r_Clk_Count_cry_5_0_S1 Net - - - - 1
|
|
uart_module.p_UART_RX\.r_Clk_Count_6_iv[6] ORCALUT4 A In 0.000 8.137 -
|
|
uart_module.p_UART_RX\.r_Clk_Count_6_iv[6] ORCALUT4 Z Out 0.617 8.754 -
|
|
r_Clk_Count_6[6] Net - - - - 1
|
|
uart_module.r_Clk_Count[6] FD1S3IX D In 0.000 8.754 -
|
|
=============================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7400_1|y1_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA0 screen_char[0] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA1 screen_char[1] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA2 screen_char[2] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA3 screen_char[3] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA4 screen_char[4] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA5 screen_char[5] 3.737 994.062
|
|
apple_module.C3.LineBuffer.FF_2 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w3 1.108 996.291
|
|
apple_module.C3.LineBuffer.FF_5 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.C3.LineBuffer.FF_3 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w2 1.108 996.859
|
|
apple_module.C3.LineBuffer.FF_4 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w1 1.108 996.859
|
|
======================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA6 screen_char[0] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA7 screen_char[1] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA8 screen_char[2] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA9 screen_char[3] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA10 screen_char[4] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA11 screen_char[5] 998.318 994.581
|
|
apple_module.C3.LineBuffer.OR2_t0 dm7400_1|y1_inferred_clock OR2 B dec0_r102 1000.000 996.291
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA3 shreg_addr_w0 998.318 997.210
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA4 shreg_addr_w1 998.318 997.210
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA5 shreg_addr_w2 998.318 997.210
|
|
======================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 998.247
|
|
|
|
- Propagation time: 4.185
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 994.062
|
|
|
|
Number of logic level(s): 1
|
|
Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA0
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA0
|
|
The start point is clocked by dm7400_1|y1_inferred_clock [rising] on pin CLKA
|
|
The end point is clocked by dm7400_1|y1_inferred_clock [rising] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
----------------------------------------------------------------------------------------------------------
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA0 Out 3.737 3.737 -
|
|
screen_char[0] Net - - - - 2
|
|
apple_module.C3.input[0] ORCALUT4 D In 0.000 3.737 -
|
|
apple_module.C3.input[0] ORCALUT4 Z Out 0.449 4.185 -
|
|
input[0] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA0 In 0.000 4.185 -
|
|
==========================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7400_1|y3_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
---------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.D13.flash_counter[1] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[1] 1.180 996.187
|
|
apple_module.D13.flash_counter[2] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[2] 1.148 996.219
|
|
apple_module.D13.flash_counter[3] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[3] 1.108 996.259
|
|
apple_module.D13.flash_counter[5] dm7400_1|y3_inferred_clock FD1S3AX Q cursor_flash 1.108 996.259
|
|
apple_module.D13.flash_counter[0] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[0] 1.188 997.195
|
|
apple_module.D13.flash_counter[4] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[4] 1.148 997.307
|
|
=================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.D13.flash_counter[5] dm7400_1|y3_inferred_clock FD1S3AX D flash_counter_3[5] 1000.089 996.187
|
|
apple_module.D13.flash_counter[4] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc4 1000.089 997.195
|
|
apple_module.D13.flash_counter[0] dm7400_1|y3_inferred_clock FD1S3AX D flash_counter_3[0] 1000.089 997.203
|
|
apple_module.D13.flash_counter[1] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc1 1000.089 998.284
|
|
apple_module.D13.flash_counter[2] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc2 1000.089 998.284
|
|
apple_module.D13.flash_counter[3] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc3 1000.089 998.284
|
|
============================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: -0.089
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 1000.089
|
|
|
|
- Propagation time: 3.902
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 996.187
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.D13.flash_counter[1] / Q
|
|
Ending point: apple_module.D13.flash_counter[5] / D
|
|
The start point is clocked by dm7400_1|y3_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400_1|y3_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------
|
|
apple_module.D13.flash_counter[1] FD1S3AX Q Out 1.180 1.180 -
|
|
flash_counter[1] Net - - - - 5
|
|
apple_module.D13.flash_counter_1_3 ORCALUT4 A In 0.000 1.180 -
|
|
apple_module.D13.flash_counter_1_3 ORCALUT4 Z Out 1.089 2.269 -
|
|
flash_counter_1_3 Net - - - - 2
|
|
apple_module.D13.flash_counter_1 ORCALUT4 C In 0.000 2.269 -
|
|
apple_module.D13.flash_counter_1 ORCALUT4 Z Out 1.017 3.285 -
|
|
flash_counter_1 Net - - - - 1
|
|
apple_module.D13.flash_counter_3[5] ORCALUT4 B In 0.000 3.285 -
|
|
apple_module.D13.flash_counter_3[5] ORCALUT4 Z Out 0.617 3.902 -
|
|
flash_counter_3[5] Net - - - - 1
|
|
apple_module.D13.flash_counter[5] FD1S3AX D In 0.000 3.902 -
|
|
======================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7427|y1_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
---------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[1] dm7427|y1_inferred_clock FD1S3AX Q char_ready 1.148 993.424
|
|
apple_module.C7.states[5] dm7427|y1_inferred_clock FD1S3AX Q wc2_i 1.044 993.977
|
|
apple_module.C7.states[3] dm7427|y1_inferred_clock FD1S3AX Q cleared_last 0.972 994.049
|
|
apple_module.C7.states[0] dm7427|y1_inferred_clock FD1S3AX Q screen_clear_inhibit 0.972 995.241
|
|
apple_module.C7.states[4] dm7427|y1_inferred_clock FD1S3AX Q line_clear_inhibit 0.972 995.690
|
|
apple_module.C11b.sram_1_0_0_0 dm7427|y1_inferred_clock DP8KC DOA0 mem_curs_out[0] 3.737 996.158
|
|
apple_module.C11b.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.D4a.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.D14b.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.D14a.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
=================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[5] dm7427|y1_inferred_clock FD1S3AX D wc1_i 999.894 995.431
|
|
apple_module.C13.states[3] dm7427|y1_inferred_clock FD1S3AX D mem_curs_out[0] 999.894 996.158
|
|
apple_module.C11b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D14a.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D4a.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D14b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D5a.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D4b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D5b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.C11b.sram_1_0_0_0 dm7427|y1_inferred_clock DP8KC DIA1 mem_curs_in[0] 998.247 996.755
|
|
=============================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
+ Estimated clock delay at ending point: 0.000
|
|
= Required time: 999.528
|
|
|
|
- Propagation time: 6.105
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 993.424
|
|
|
|
Number of logic level(s): 6
|
|
Starting point: apple_module.C7.states[1] / Q
|
|
Ending point: apple_module.D8.count[0] / SP
|
|
The start point is clocked by dm7427|y1_inferred_clock [rising] on pin CK
|
|
The end point is clocked by System [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-----------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[1] FD1S3AX Q Out 1.148 1.148 -
|
|
char_ready Net - - - - 4
|
|
apple_module.C5.y2 ORCALUT4 B In 0.000 1.148 -
|
|
apple_module.C5.y2 ORCALUT4 Z Out 0.449 1.597 -
|
|
y2_0 Net - - - - 2
|
|
apple_module.C8.un1_y2 ORCALUT4 A In 0.000 1.597 -
|
|
apple_module.C8.un1_y2 ORCALUT4 Z Out 1.193 2.789 -
|
|
clear_char Net - - - - 4
|
|
apple_module.C8.un6_y1 ORCALUT4 B In 0.000 2.789 -
|
|
apple_module.C8.un6_y1 ORCALUT4 Z Out 0.449 3.238 -
|
|
un6_y1 Net - - - - 1
|
|
apple_module.C12.Y2 ORCALUT4 A In 0.000 3.238 -
|
|
apple_module.C12.Y2 ORCALUT4 Z Out 1.225 4.463 -
|
|
wc1_i Net - - - - 5
|
|
apple_module.C12.Y2_RNICBVQ ORCALUT4 B In 0.000 4.463 -
|
|
apple_module.C12.Y2_RNICBVQ ORCALUT4 Z Out 0.449 4.912 -
|
|
load_v_i_0 Net - - - - 5
|
|
apple_module.D8.count_cnv[0] ORCALUT4 C In 0.000 4.912 -
|
|
apple_module.D8.count_cnv[0] ORCALUT4 Z Out 1.193 6.105 -
|
|
count_cnv_0[0] Net - - - - 4
|
|
apple_module.D8.count[0] FD1P3DX SP In 0.000 6.105 -
|
|
===============================================================================================
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====================================
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Detailed Report for Clock: System
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Clock
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------------------------------------------------------------------------------------------------------------
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apple_module.C13.states[3] System FD1S3AX Q states[3] 1.180 993.392
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apple_module.D7.count[3] System FD1P3AX Q horz_count_upper[3] 1.232 994.084
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apple_module.D9.count[3] System FD1P3DX Q count_0[3] 1.148 994.168
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apple_module.D9.count[2] System FD1P3DX Q count_0[2] 1.108 994.208
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apple_module.D9.count[1] System FD1P3DX Q count[1] 1.148 994.946
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apple_module.D8.count[0] System FD1P3DX Q count[0] 1.204 995.026
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apple_module.D8.count[1] System FD1P3DX Q count[1] 1.188 995.042
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apple_module.D6.count[3] System FD1P3AX Q horz_count_lower[3] 1.220 995.474
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apple_module.D7.count[2] System FD1P3AX Q horz_count_upper[2] 1.220 995.514
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apple_module.D7.count[0] System FD1P3AX Q horz_count_upper[0] 1.188 995.546
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============================================================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Clock
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-----------------------------------------------------------------------------------------------------
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apple_module.C7.states[5] System FD1S3AX D wc1_i 999.894 995.399
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apple_module.D1.Qd System FD1P3AX D Qd_3 1000.089 995.735
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apple_module.D1.Qe System FD1P3AX D Qe_3 1000.089 995.735
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apple_module.D1.Qf System FD1P3AX D Qf_3 1000.089 995.735
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apple_module.D1.Qg System FD1P3AX D Qg_3 1000.089 995.735
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apple_module.D1.Qh System FD1P3AX D Qh_3 1000.089 995.735
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apple_module.D7.count[0] System FD1P3AX SP count_cnv[0] 999.528 995.923
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apple_module.D7.count[1] System FD1P3AX SP count_cnv[0] 999.528 995.923
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apple_module.D7.count[2] System FD1P3AX SP count_cnv[0] 999.528 995.923
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apple_module.D7.count[3] System FD1P3AX SP count_cnv[0] 999.528 995.923
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=====================================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 1000.000
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- Setup time: 0.472
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+ Clock delay at ending point: 0.000 (ideal)
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+ Estimated clock delay at ending point: 0.000
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= Required time: 999.528
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- Propagation time: 6.137
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- Clock delay at starting point: 0.000 (ideal)
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- Estimated clock delay at start point: -0.000
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= Slack (non-critical) : 993.392
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Number of logic level(s): 6
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Starting point: apple_module.C13.states[3] / Q
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Ending point: apple_module.D8.count[0] / SP
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The start point is clocked by System [rising] on pin CK
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The end point is clocked by System [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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-----------------------------------------------------------------------------------------------
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apple_module.C13.states[3] FD1S3AX Q Out 1.180 1.180 -
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states[3] Net - - - - 5
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apple_module.C5.y2 ORCALUT4 A In 0.000 1.180 -
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apple_module.C5.y2 ORCALUT4 Z Out 0.449 1.629 -
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y2_0 Net - - - - 2
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apple_module.C8.un1_y2 ORCALUT4 A In 0.000 1.629 -
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apple_module.C8.un1_y2 ORCALUT4 Z Out 1.193 2.821 -
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clear_char Net - - - - 4
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apple_module.C8.un6_y1 ORCALUT4 B In 0.000 2.821 -
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apple_module.C8.un6_y1 ORCALUT4 Z Out 0.449 3.270 -
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un6_y1 Net - - - - 1
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apple_module.C12.Y2 ORCALUT4 A In 0.000 3.270 -
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apple_module.C12.Y2 ORCALUT4 Z Out 1.225 4.495 -
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wc1_i Net - - - - 5
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apple_module.C12.Y2_RNICBVQ ORCALUT4 B In 0.000 4.495 -
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apple_module.C12.Y2_RNICBVQ ORCALUT4 Z Out 0.449 4.944 -
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load_v_i_0 Net - - - - 5
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apple_module.D8.count_cnv[0] ORCALUT4 C In 0.000 4.944 -
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apple_module.D8.count_cnv[0] ORCALUT4 Z Out 1.193 6.137 -
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count_cnv_0[0] Net - - - - 4
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apple_module.D8.count[0] FD1P3DX SP In 0.000 6.137 -
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===============================================================================================
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##### END OF TIMING REPORT #####]
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Timing exceptions that could not be applied
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None
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Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 150MB)
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Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 150MB)
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---------------------------------------
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Resource Usage Report
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Part: lcmxo2_7000hc-4
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Register bits: 175 of 6864 (3%)
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PIC Latch: 0
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I/O cells: 15
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Block Rams : 9 of 26 (34%)
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Details:
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CCU2D: 17
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CU2: 38
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DP8KC: 9
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FADD2B: 8
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FD1P3AX: 49
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FD1P3DX: 8
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FD1P3IX: 76
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FD1P3JX: 7
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FD1S3AX: 22
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FD1S3IX: 12
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GSR: 1
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IB: 3
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IFS1P3DX: 1
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INV: 25
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OB: 12
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OR2: 8
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ORCALUT4: 143
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PFUMX: 3
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PUR: 1
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ROM16X1A: 30
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VHI: 34
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VLO: 34
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 150MB)
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Process took 0h:00m:02s realtime, 0h:00m:02s cputime
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# Thu Aug 8 18:39:15 2019
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###########################################################]
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