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Apple1Display
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Apple1Display/impl1/Apple1Display_impl1.tw1

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Loading design for application trce from file apple1display_impl1_map.ncd.
Design name: FleaFPGA_Uno_E1
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.10.2.115
Thu Aug 08 18:39:21 2019
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Apple1Display_impl1.tw1 -gui -msgset C:/Dev/Apple1Display/promote.xml Apple1Display_impl1_map.ncd Apple1Display_impl1.prf
Design file: apple1display_impl1_map.ncd
Preference file: apple1display_impl1.prf
Device,speed: LCMXO2-7000HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
1257 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 28.412ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q flash_count[3] (from sys_clock_c +)
Destination: FF Data in rd[5] (to sys_clock_c +)
FF rd[4]
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
Constraint Details:
11.306ns physical path delay SLICE_61 to SLICE_121 meets
40.000ns delay constraint less
0.282ns CE_SET requirement (totaling 39.718ns) by 28.412ns
Physical Path Details:
Data path SLICE_61 to SLICE_121:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from sys_clock_c)
ROUTE 2 e 1.234 SLICE_61.Q0 to SLICE_147.B1 flash_count[3]
CTOF_DEL --- 0.495 SLICE_147.B1 to SLICE_147.F1 SLICE_147
ROUTE 1 e 0.480 SLICE_147.F1 to SLICE_147.D0 un1_flash_countlto4_1
CTOF_DEL --- 0.495 SLICE_147.D0 to SLICE_147.F0 SLICE_147
ROUTE 1 e 1.234 SLICE_147.F0 to SLICE_120.B0 un1_flash_countlt9
CTOF_DEL --- 0.495 SLICE_120.B0 to SLICE_120.F0 SLICE_120
ROUTE 1 e 1.234 SLICE_120.F0 to SLICE_156.D1 un1_flash_countlt14
CTOF_DEL --- 0.495 SLICE_156.D1 to SLICE_156.F1 SLICE_156
ROUTE 1 e 1.234 SLICE_156.F1 to SLICE_122.C1 un1_flash_countlt21
CTOF_DEL --- 0.495 SLICE_122.C1 to SLICE_122.F1 SLICE_122
ROUTE 19 e 1.234 SLICE_122.F1 to SLICE_94.C1 un1_flash_countlt22
CTOF_DEL --- 0.495 SLICE_94.C1 to SLICE_94.F1 SLICE_94
ROUTE 4 e 1.234 SLICE_94.F1 to SLICE_121.CE un1_flash_count_1 (to sys_clock_c)
--------
11.306 (30.3% logic, 69.7% route), 7 logic levels.
Report: 86.296MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
899 items scored, 204 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 2.563ns (weighted slack = -17.941ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rd[0] (from sys_clock_c +)
Destination: FF Data in apple_module/D8/count[1] (to circuit_clk +)
FF apple_module/D8/count[0]
Delay: 12.281ns (31.9% logic, 68.1% route), 8 logic levels.
Constraint Details:
12.281ns physical path delay SLICE_122 to apple_module/D8/SLICE_78 exceeds
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
10.000ns delay constraint less
0.282ns CE_SET requirement (totaling 9.718ns) by 2.563ns
Physical Path Details:
Data path SLICE_122 to apple_module/D8/SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_122.CLK to SLICE_122.Q0 SLICE_122 (from sys_clock_c)
ROUTE 2 e 1.234 SLICE_122.Q0 to */SLICE_126.A1 rd[0]
CTOF_DEL --- 0.495 */SLICE_126.A1 to */SLICE_126.F1 apple_module/C8/SLICE_126
ROUTE 1 e 0.480 */SLICE_126.F1 to */SLICE_126.A0 apple_module/C8/y2_1
CTOF_DEL --- 0.495 */SLICE_126.A0 to */SLICE_126.F0 apple_module/C8/SLICE_126
ROUTE 1 e 1.234 */SLICE_126.F0 to *e/SLICE_77.B0 apple_module/C8/y2_3
CTOF_DEL --- 0.495 *e/SLICE_77.B0 to *e/SLICE_77.F0 apple_module/SLICE_77
ROUTE 4 e 1.234 *e/SLICE_77.F0 to *e/SLICE_93.B1 apple_module/clear_char
CTOF_DEL --- 0.495 *e/SLICE_93.B1 to *e/SLICE_93.F1 apple_module/SLICE_93
ROUTE 1 e 0.480 *e/SLICE_93.F1 to *e/SLICE_93.A0 apple_module/un6_y1
CTOF_DEL --- 0.495 *e/SLICE_93.A0 to *e/SLICE_93.F0 apple_module/SLICE_93
ROUTE 5 e 1.234 *e/SLICE_93.F0 to */SLICE_152.D1 apple_module/wc1_i
CTOF_DEL --- 0.495 */SLICE_152.D1 to */SLICE_152.F1 apple_module/SLICE_152
ROUTE 5 e 1.234 */SLICE_152.F1 to */SLICE_141.C1 apple_module/load_v_i_0
CTOF_DEL --- 0.495 */SLICE_141.C1 to */SLICE_141.F1 apple_module/SLICE_141
ROUTE 2 e 1.234 */SLICE_141.F1 to *8/SLICE_78.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
--------
12.281 (31.9% logic, 68.1% route), 8 logic levels.
Warning: 11.371MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
1120 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.228ns (weighted slack = 4.912ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/C13/states[3] (from circuit_clk +)
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
Delay: 8.823ns (33.2% logic, 66.8% route), 6 logic levels.
Constraint Details:
8.823ns physical path delay apple_module/SLICE_90 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
10.000ns delay constraint less
-0.051ns DATA_SET requirement (totaling 10.051ns) by 1.228ns
Physical Path Details:
Data path apple_module/SLICE_90 to apple_module/C3/LineBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 */SLICE_90.CLK to *e/SLICE_90.Q1 apple_module/SLICE_90 (from circuit_clk)
ROUTE 5 e 0.480 *e/SLICE_90.Q1 to *e/SLICE_90.A1 apple_module/states[3]
CTOF_DEL --- 0.495 *e/SLICE_90.A1 to *e/SLICE_90.F1 apple_module/SLICE_90
ROUTE 2 e 1.234 *e/SLICE_90.F1 to *e/SLICE_77.A0 apple_module/y2_1
CTOF_DEL --- 0.495 *e/SLICE_77.A0 to *e/SLICE_77.F0 apple_module/SLICE_77
ROUTE 4 e 0.480 *e/SLICE_77.F0 to *e/SLICE_77.B1 apple_module/clear_char
CTOF_DEL --- 0.495 *e/SLICE_77.B1 to *e/SLICE_77.F1 apple_module/SLICE_77
ROUTE 8 e 1.234 *e/SLICE_77.F1 to */SLICE_117.C1 apple_module/clr
CTOF_DEL --- 0.495 */SLICE_117.C1 to */SLICE_117.F1 apple_module/SLICE_117
ROUTE 1 e 1.234 */SLICE_117.F1 to */SLICE_128.C1 apple_module/msb
CTOF_DEL --- 0.495 */SLICE_128.C1 to */SLICE_128.F1 apple_module/SLICE_128
ROUTE 1 e 1.234 */SLICE_128.F1 to *_1_0_0_0.DIA5 apple_module/C3/input[5] (to apple_module/D10/y1)
--------
8.823 (33.2% logic, 66.8% route), 6 logic levels.
Report: 28.500MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sys_clock_c" 25.000000 | | |
MHz ; | 25.000 MHz| 86.296 MHz| 7
| | |
FREQUENCY NET "circuit_clk" 14.285714 | | |
MHz ; | 14.286 MHz| 11.371 MHz| 8 *
| | |
FREQUENCY PORT "sys_clock" 25.000000 | | |
MHz ; | 25.000 MHz| 28.500 MHz| 6
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
apple_module/wc1_i | 5| 204| 100.00%
| | |
apple_module/clear_char | 4| 204| 100.00%
| | |
apple_module/un6_y1 | 1| 144| 70.59%
| | |
apple_module/C8/y2_3 | 1| 138| 67.65%
| | |
apple_module/load_v_i_0 | 5| 94| 46.08%
| | |
apple_module/C8/y2_1 | 1| 72| 35.29%
| | |
apple_module/y2_1 | 2| 66| 32.35%
| | |
apple_module/D8/N_19 | 4| 40| 19.61%
| | |
apple_module/count_5[0] | 4| 40| 19.61%
| | |
rd[3] | 2| 36| 17.65%
| | |
rd[0] | 2| 36| 17.65%
| | |
apple_module/D8/count_cnv_0[0] | 2| 32| 15.69%
| | |
apple_module/D9/count_cnv_1[0] | 2| 32| 15.69%
| | |
apple_module/D9/N_19 | 3| 30| 14.71%
| | |
rd[4] | 2| 22| 10.78%
| | |
rd[2] | 2| 22| 10.78%
| | |
rd[1] | 2| 22| 10.78%
| | |
rd[5] | 2| 22| 10.78%
| | |
apple_module/char_ready | 4| 22| 10.78%
| | |
rd[6] | 3| 22| 10.78%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 8 clocks:
Clock Domain: clock_module/CLKFB_t Source: clock_module/PLLInst_0.CLKINTFB Loads: 1
No transfer within this clock domain is found
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
No transfer within this clock domain is found
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: sys_clock_c Source: sys_clock.PAD
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
No transfer within this clock domain is found
Data transfers from:
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 18
Clock Domain: sys_clock_c Source: sys_clock.PAD
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
No transfer within this clock domain is found
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 24
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
Data transfers from:
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 6
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 4
Clock Domain: sys_clock_c Source: sys_clock.PAD
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 7
Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 38
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
Data transfers from:
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ; Transfers: 1
Timing summary (Setup):
---------------
Timing errors: 204 Score: 1027544
Cumulative negative slack: 1027544
Constraints cover 3276 paths, 10 nets, and 1222 connections (98.39% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.2.115
Thu Aug 08 18:39:21 2019
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Apple1Display_impl1.tw1 -gui -msgset C:/Dev/Apple1Display/promote.xml Apple1Display_impl1_map.ncd Apple1Display_impl1.prf
Design file: apple1display_impl1_map.ncd
Preference file: apple1display_impl1.prf
Device,speed: LCMXO2-7000HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
1257 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.441ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q uart_module/r_SM_Main[1] (from sys_clock_c +)
Destination: FF Data in uart_module/r_SM_Main[1] (to sys_clock_c +)
Delay: 0.428ns (53.3% logic, 46.7% route), 2 logic levels.
Constraint Details:
0.428ns physical path delay uart_module/SLICE_115 to uart_module/SLICE_115 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.441ns
Physical Path Details:
Data path uart_module/SLICE_115 to uart_module/SLICE_115:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_115.CLK to */SLICE_115.Q0 uart_module/SLICE_115 (from sys_clock_c)
ROUTE 9 e 0.199 */SLICE_115.Q0 to */SLICE_115.M0 uart_module/r_SM_Main[1]
MTOOFX_DEL --- 0.095 */SLICE_115.M0 to *LICE_115.OFX0 uart_module/SLICE_115
ROUTE 1 e 0.001 *LICE_115.OFX0 to *SLICE_115.DI0 uart_module/r_SM_Main_ns[1] (to sys_clock_c)
--------
0.428 (53.3% logic, 46.7% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
899 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/D15/count[0] (from circuit_clk +)
Destination: FF Data in apple_module/D15/count[2] (to circuit_clk +)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay apple_module/D15/SLICE_71 to apple_module/D15/SLICE_71 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path apple_module/D15/SLICE_71 to apple_module/D15/SLICE_71:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 */SLICE_71.CLK to *5/SLICE_71.Q0 apple_module/D15/SLICE_71 (from circuit_clk)
ROUTE 4 e 0.199 *5/SLICE_71.Q0 to *5/SLICE_71.B1 apple_module/D15/count[0]
CTOF_DEL --- 0.101 *5/SLICE_71.B1 to *5/SLICE_71.F1 apple_module/D15/SLICE_71
ROUTE 1 e 0.001 *5/SLICE_71.F1 to */SLICE_71.DI1 apple_module/D15/N_42_i (to circuit_clk)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
1120 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q apple_module/D13/flash_counter[1] (from apple_module/D10/y3 +)
Destination: FF Data in apple_module/D13/flash_counter[1] (to apple_module/D10/y3 +)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay apple_module/D13/SLICE_68 to apple_module/D13/SLICE_68 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path apple_module/D13/SLICE_68 to apple_module/D13/SLICE_68:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 */SLICE_68.CLK to *3/SLICE_68.Q1 apple_module/D13/SLICE_68 (from apple_module/D10/y3)
ROUTE 5 e 0.199 *3/SLICE_68.Q1 to *3/SLICE_68.B1 apple_module/D13/flash_counter[1]
CTOF_DEL --- 0.101 *3/SLICE_68.B1 to *3/SLICE_68.F1 apple_module/D13/SLICE_68
ROUTE 1 e 0.001 *3/SLICE_68.F1 to */SLICE_68.DI1 apple_module/D13/un3_flash_counter_1_axbxc1 (to apple_module/D10/y3)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sys_clock_c" 25.000000 | | |
MHz ; | 0.000 ns| 0.441 ns| 2
| | |
FREQUENCY NET "circuit_clk" 14.285714 | | |
MHz ; | 0.000 ns| 0.447 ns| 2
| | |
FREQUENCY PORT "sys_clock" 25.000000 | | |
MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 8 clocks:
Clock Domain: clock_module/CLKFB_t Source: clock_module/PLLInst_0.CLKINTFB Loads: 1
No transfer within this clock domain is found
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
No transfer within this clock domain is found
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: sys_clock_c Source: sys_clock.PAD
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
No transfer within this clock domain is found
Data transfers from:
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 18
Clock Domain: sys_clock_c Source: sys_clock.PAD
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
No transfer within this clock domain is found
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 24
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
Data transfers from:
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 6
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 4
Clock Domain: sys_clock_c Source: sys_clock.PAD
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 7
Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 38
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
Data transfers from:
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ; Transfers: 1
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 3276 paths, 10 nets, and 1222 connections (98.39% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 204 (setup), 0 (hold)
Score: 1027544 (setup), 0 (hold)
Cumulative negative slack: 1027544 (1027544+0)
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