4443 lines
210 KiB
Plaintext
4443 lines
210 KiB
Plaintext
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Loading design for application trce from file apple1display_impl1.ncd.
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Design name: FleaFPGA_Uno_E1
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-7000HC
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Package: TQFP144
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Performance: 4
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Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.10.2.115
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Thu Aug 08 18:39:39 2019
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Apple1Display_impl1.twr -gui -msgset C:/Dev/Apple1Display/promote.xml Apple1Display_impl1.ncd Apple1Display_impl1.prf
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Design file: apple1display_impl1.ncd
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Preference file: apple1display_impl1.prf
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Device,speed: LCMXO2-7000HC,4
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Report level: verbose report, limited to 10 items per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
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1257 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 4.122ns (weighted slack = 8.244ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C7/states[2] (from apple_module/C5/y1 -)
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Destination: FF Data in da (to sys_clock_c +)
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Delay: 4.803ns (19.7% logic, 80.3% route), 2 logic levels.
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Constraint Details:
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4.803ns physical path delay apple_module/SLICE_100 to SLICE_94 meets
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20.000ns delay constraint less
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10.801ns skew and
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0.000ns feedback compensation and
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0.274ns LSR_SET requirement (totaling 8.925ns) by 4.122ns
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Physical Path Details:
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Data path apple_module/SLICE_100 to SLICE_94:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q0 apple_module/SLICE_100 (from apple_module/C5/y1)
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ROUTE 3 1.933 R21C30C.Q0 to R21C21B.A0 rda_i
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CTOF_DEL --- 0.495 R21C21B.A0 to R21C21B.F0 SLICE_122
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ROUTE 1 1.923 R21C21B.F0 to R21C26D.LSR da_0_sqmuxa (to sys_clock_c)
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--------
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4.803 (19.7% logic, 80.3% route), 2 logic levels.
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Clock Skew Details:
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Source Clock Path sys_clock to apple_module/SLICE_100:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
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CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
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ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
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REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
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ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
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CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
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ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
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CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
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ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
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--------
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14.456 (17.8% logic, 82.2% route), 5 logic levels.
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Source Clock f/b:
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Name Fanout Delay (ns) Site Resource
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CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
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ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
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--------
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0.000 (0.0% logic, 0.0% route), 1 logic levels.
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Destination Clock Path sys_clock to SLICE_94:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 2.523 126.PADDI to R21C26D.CLK sys_clock_c
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--------
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3.655 (31.0% logic, 69.0% route), 1 logic levels.
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Passed: The following path meets requirements by 4.859ns (weighted slack = 9.718ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C7/states[2] (from apple_module/C5/y1 -)
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Destination: FF Data in rd[1] (to sys_clock_c +)
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FF rd[0]
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Delay: 4.058ns (23.3% logic, 76.7% route), 2 logic levels.
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Constraint Details:
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4.058ns physical path delay apple_module/SLICE_100 to SLICE_122 meets
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20.000ns delay constraint less
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10.801ns skew and
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0.000ns feedback compensation and
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0.282ns CE_SET requirement (totaling 8.917ns) by 4.859ns
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Physical Path Details:
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Data path apple_module/SLICE_100 to SLICE_122:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q0 apple_module/SLICE_100 (from apple_module/C5/y1)
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ROUTE 3 1.513 R21C30C.Q0 to R21C26D.A1 rda_i
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CTOF_DEL --- 0.495 R21C26D.A1 to R21C26D.F1 SLICE_94
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ROUTE 4 1.598 R21C26D.F1 to R21C21B.CE un1_flash_count_1 (to sys_clock_c)
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--------
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4.058 (23.3% logic, 76.7% route), 2 logic levels.
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Clock Skew Details:
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Source Clock Path sys_clock to apple_module/SLICE_100:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
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CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
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ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
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REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
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ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
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CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
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ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
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CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
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ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
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--------
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14.456 (17.8% logic, 82.2% route), 5 logic levels.
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Source Clock f/b:
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Name Fanout Delay (ns) Site Resource
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CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
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ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
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--------
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0.000 (0.0% logic, 0.0% route), 1 logic levels.
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Destination Clock Path sys_clock to SLICE_122:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 2.523 126.PADDI to R21C21B.CLK sys_clock_c
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--------
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3.655 (31.0% logic, 69.0% route), 1 logic levels.
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Passed: The following path meets requirements by 5.356ns (weighted slack = 10.712ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C7/states[2] (from apple_module/C5/y1 -)
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Destination: FF Data in rd[5] (to sys_clock_c +)
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FF rd[4]
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Delay: 3.561ns (26.6% logic, 73.4% route), 2 logic levels.
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Constraint Details:
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3.561ns physical path delay apple_module/SLICE_100 to SLICE_121 meets
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20.000ns delay constraint less
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10.801ns skew and
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0.000ns feedback compensation and
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0.282ns CE_SET requirement (totaling 8.917ns) by 5.356ns
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Physical Path Details:
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Data path apple_module/SLICE_100 to SLICE_121:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q0 apple_module/SLICE_100 (from apple_module/C5/y1)
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ROUTE 3 1.513 R21C30C.Q0 to R21C26D.A1 rda_i
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CTOF_DEL --- 0.495 R21C26D.A1 to R21C26D.F1 SLICE_94
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ROUTE 4 1.101 R21C26D.F1 to R21C28C.CE un1_flash_count_1 (to sys_clock_c)
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--------
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3.561 (26.6% logic, 73.4% route), 2 logic levels.
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Clock Skew Details:
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Source Clock Path sys_clock to apple_module/SLICE_100:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
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CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
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ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
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REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
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ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
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CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
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ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
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CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
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ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
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--------
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14.456 (17.8% logic, 82.2% route), 5 logic levels.
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Source Clock f/b:
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Name Fanout Delay (ns) Site Resource
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CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
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ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
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--------
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0.000 (0.0% logic, 0.0% route), 1 logic levels.
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Destination Clock Path sys_clock to SLICE_121:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 2.523 126.PADDI to R21C28C.CLK sys_clock_c
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--------
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3.655 (31.0% logic, 69.0% route), 1 logic levels.
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Passed: The following path meets requirements by 5.356ns (weighted slack = 10.712ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C7/states[2] (from apple_module/C5/y1 -)
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Destination: FF Data in rd[3] (to sys_clock_c +)
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FF rd[2]
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Delay: 3.561ns (26.6% logic, 73.4% route), 2 logic levels.
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Constraint Details:
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3.561ns physical path delay apple_module/SLICE_100 to SLICE_124 meets
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20.000ns delay constraint less
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10.801ns skew and
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0.000ns feedback compensation and
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0.282ns CE_SET requirement (totaling 8.917ns) by 5.356ns
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Physical Path Details:
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Data path apple_module/SLICE_100 to SLICE_124:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q0 apple_module/SLICE_100 (from apple_module/C5/y1)
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ROUTE 3 1.513 R21C30C.Q0 to R21C26D.A1 rda_i
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CTOF_DEL --- 0.495 R21C26D.A1 to R21C26D.F1 SLICE_94
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ROUTE 4 1.101 R21C26D.F1 to R21C28B.CE un1_flash_count_1 (to sys_clock_c)
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--------
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3.561 (26.6% logic, 73.4% route), 2 logic levels.
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Clock Skew Details:
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Source Clock Path sys_clock to apple_module/SLICE_100:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
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CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
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ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
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REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
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ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
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CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
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ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
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CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
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ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
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--------
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14.456 (17.8% logic, 82.2% route), 5 logic levels.
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Source Clock f/b:
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Name Fanout Delay (ns) Site Resource
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CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
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ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
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--------
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0.000 (0.0% logic, 0.0% route), 1 logic levels.
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Destination Clock Path sys_clock to SLICE_124:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 2.523 126.PADDI to R21C28B.CLK sys_clock_c
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--------
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3.655 (31.0% logic, 69.0% route), 1 logic levels.
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Passed: The following path meets requirements by 5.787ns (weighted slack = 11.574ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C7/states[2] (from apple_module/C5/y1 -)
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Destination: FF Data in rd[6] (to sys_clock_c +)
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Delay: 3.130ns (30.3% logic, 69.7% route), 2 logic levels.
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Constraint Details:
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3.130ns physical path delay apple_module/SLICE_100 to SLICE_149 meets
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20.000ns delay constraint less
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10.801ns skew and
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0.000ns feedback compensation and
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0.282ns CE_SET requirement (totaling 8.917ns) by 5.787ns
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Physical Path Details:
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Data path apple_module/SLICE_100 to SLICE_149:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q0 apple_module/SLICE_100 (from apple_module/C5/y1)
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ROUTE 3 1.513 R21C30C.Q0 to R21C26D.A1 rda_i
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CTOF_DEL --- 0.495 R21C26D.A1 to R21C26D.F1 SLICE_94
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ROUTE 4 0.670 R21C26D.F1 to R21C26A.CE un1_flash_count_1 (to sys_clock_c)
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--------
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3.130 (30.3% logic, 69.7% route), 2 logic levels.
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Clock Skew Details:
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Source Clock Path sys_clock to apple_module/SLICE_100:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
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CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
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ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
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REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
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ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
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CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
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ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
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CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
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ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
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--------
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14.456 (17.8% logic, 82.2% route), 5 logic levels.
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Source Clock f/b:
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Name Fanout Delay (ns) Site Resource
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CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
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ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
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--------
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0.000 (0.0% logic, 0.0% route), 1 logic levels.
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Destination Clock Path sys_clock to SLICE_149:
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Name Fanout Delay (ns) Site Resource
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PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
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ROUTE 38 2.523 126.PADDI to R21C26A.CLK sys_clock_c
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--------
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3.655 (31.0% logic, 69.0% route), 1 logic levels.
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Passed: The following path meets requirements by 6.573ns (weighted slack = 13.146ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C7/states[2] (from apple_module/C5/y1 -)
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Destination: FF Data in da (to sys_clock_c +)
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Delay: 2.460ns (38.5% logic, 61.5% route), 2 logic levels.
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Constraint Details:
|
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2.460ns physical path delay apple_module/SLICE_100 to SLICE_94 meets
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20.000ns delay constraint less
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|
10.801ns skew and
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0.000ns feedback compensation and
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0.166ns DIN_SET requirement (totaling 9.033ns) by 6.573ns
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Physical Path Details:
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Data path apple_module/SLICE_100 to SLICE_94:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q0 apple_module/SLICE_100 (from apple_module/C5/y1)
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ROUTE 3 1.513 R21C30C.Q0 to R21C26D.A0 rda_i
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CTOF_DEL --- 0.495 R21C26D.A0 to R21C26D.F0 SLICE_94
|
|
ROUTE 1 0.000 R21C26D.F0 to R21C26D.DI0 da.fb_0 (to sys_clock_c)
|
|
--------
|
|
2.460 (38.5% logic, 61.5% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_94:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 2.523 126.PADDI to R21C26D.CLK sys_clock_c
|
|
--------
|
|
3.655 (31.0% logic, 69.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 27.501ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[2] (from sys_clock_c +)
|
|
Destination: FF Data in rd[1] (to sys_clock_c +)
|
|
FF rd[0]
|
|
|
|
Delay: 12.180ns (28.1% logic, 71.9% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
12.180ns physical path delay SLICE_62 to SLICE_122 meets
|
|
40.000ns delay constraint less
|
|
0.037ns skew and
|
|
0.282ns CE_SET requirement (totaling 39.681ns) by 27.501ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_62 to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R18C20B.CLK to R18C20B.Q1 SLICE_62 (from sys_clock_c)
|
|
ROUTE 2 1.030 R18C20B.Q1 to R19C20C.B1 flash_count[2]
|
|
CTOF_DEL --- 0.495 R19C20C.B1 to R19C20C.F1 SLICE_147
|
|
ROUTE 1 0.436 R19C20C.F1 to R19C20C.C0 un1_flash_countlto4_1
|
|
CTOF_DEL --- 0.495 R19C20C.C0 to R19C20C.F0 SLICE_147
|
|
ROUTE 1 0.744 R19C20C.F0 to R19C21C.C0 un1_flash_countlt9
|
|
CTOF_DEL --- 0.495 R19C21C.C0 to R19C21C.F0 SLICE_120
|
|
ROUTE 1 0.315 R19C21C.F0 to R19C21A.D1 un1_flash_countlt14
|
|
CTOF_DEL --- 0.495 R19C21A.D1 to R19C21A.F1 SLICE_156
|
|
ROUTE 1 1.088 R19C21A.F1 to R21C21B.B1 un1_flash_countlt21
|
|
CTOF_DEL --- 0.495 R21C21B.B1 to R21C21B.F1 SLICE_122
|
|
ROUTE 19 3.547 R21C21B.F1 to R21C26D.C1 un1_flash_countlt22
|
|
CTOF_DEL --- 0.495 R21C26D.C1 to R21C26D.F1 SLICE_94
|
|
ROUTE 4 1.598 R21C26D.F1 to R21C21B.CE un1_flash_count_1 (to sys_clock_c)
|
|
--------
|
|
12.180 (28.1% logic, 71.9% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_62:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.560 126.PADDI to R18C20B.CLK sys_clock_c
|
|
--------
|
|
2.560 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.523 126.PADDI to R21C21B.CLK sys_clock_c
|
|
--------
|
|
2.523 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 27.642ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[6] (from sys_clock_c +)
|
|
Destination: FF Data in rd[1] (to sys_clock_c +)
|
|
FF rd[0]
|
|
|
|
Delay: 12.039ns (24.3% logic, 75.7% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
12.039ns physical path delay SLICE_60 to SLICE_122 meets
|
|
40.000ns delay constraint less
|
|
0.037ns skew and
|
|
0.282ns CE_SET requirement (totaling 39.681ns) by 27.642ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_60 to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R18C20D.CLK to R18C20D.Q1 SLICE_60 (from sys_clock_c)
|
|
ROUTE 2 1.597 R18C20D.Q1 to R19C21C.C1 flash_count[6]
|
|
CTOF_DEL --- 0.495 R19C21C.C1 to R19C21C.F1 SLICE_120
|
|
ROUTE 1 0.967 R19C21C.F1 to R19C21C.A0 un1_flash_countlto13_1
|
|
CTOF_DEL --- 0.495 R19C21C.A0 to R19C21C.F0 SLICE_120
|
|
ROUTE 1 0.315 R19C21C.F0 to R19C21A.D1 un1_flash_countlt14
|
|
CTOF_DEL --- 0.495 R19C21A.D1 to R19C21A.F1 SLICE_156
|
|
ROUTE 1 1.088 R19C21A.F1 to R21C21B.B1 un1_flash_countlt21
|
|
CTOF_DEL --- 0.495 R21C21B.B1 to R21C21B.F1 SLICE_122
|
|
ROUTE 19 3.547 R21C21B.F1 to R21C26D.C1 un1_flash_countlt22
|
|
CTOF_DEL --- 0.495 R21C26D.C1 to R21C26D.F1 SLICE_94
|
|
ROUTE 4 1.598 R21C26D.F1 to R21C21B.CE un1_flash_count_1 (to sys_clock_c)
|
|
--------
|
|
12.039 (24.3% logic, 75.7% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_60:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.560 126.PADDI to R18C20D.CLK sys_clock_c
|
|
--------
|
|
2.560 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.523 126.PADDI to R21C21B.CLK sys_clock_c
|
|
--------
|
|
2.523 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 27.758ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[3] (from sys_clock_c +)
|
|
Destination: FF Data in rd[1] (to sys_clock_c +)
|
|
FF rd[0]
|
|
|
|
Delay: 11.923ns (28.7% logic, 71.3% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.923ns physical path delay SLICE_61 to SLICE_122 meets
|
|
40.000ns delay constraint less
|
|
0.037ns skew and
|
|
0.282ns CE_SET requirement (totaling 39.681ns) by 27.758ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_61 to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R18C20C.CLK to R18C20C.Q0 SLICE_61 (from sys_clock_c)
|
|
ROUTE 2 0.773 R18C20C.Q0 to R19C20C.C1 flash_count[3]
|
|
CTOF_DEL --- 0.495 R19C20C.C1 to R19C20C.F1 SLICE_147
|
|
ROUTE 1 0.436 R19C20C.F1 to R19C20C.C0 un1_flash_countlto4_1
|
|
CTOF_DEL --- 0.495 R19C20C.C0 to R19C20C.F0 SLICE_147
|
|
ROUTE 1 0.744 R19C20C.F0 to R19C21C.C0 un1_flash_countlt9
|
|
CTOF_DEL --- 0.495 R19C21C.C0 to R19C21C.F0 SLICE_120
|
|
ROUTE 1 0.315 R19C21C.F0 to R19C21A.D1 un1_flash_countlt14
|
|
CTOF_DEL --- 0.495 R19C21A.D1 to R19C21A.F1 SLICE_156
|
|
ROUTE 1 1.088 R19C21A.F1 to R21C21B.B1 un1_flash_countlt21
|
|
CTOF_DEL --- 0.495 R21C21B.B1 to R21C21B.F1 SLICE_122
|
|
ROUTE 19 3.547 R21C21B.F1 to R21C26D.C1 un1_flash_countlt22
|
|
CTOF_DEL --- 0.495 R21C26D.C1 to R21C26D.F1 SLICE_94
|
|
ROUTE 4 1.598 R21C26D.F1 to R21C21B.CE un1_flash_count_1 (to sys_clock_c)
|
|
--------
|
|
11.923 (28.7% logic, 71.3% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_61:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.560 126.PADDI to R18C20C.CLK sys_clock_c
|
|
--------
|
|
2.560 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.523 126.PADDI to R21C21B.CLK sys_clock_c
|
|
--------
|
|
2.523 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 27.812ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[8] (from sys_clock_c +)
|
|
Destination: FF Data in rd[1] (to sys_clock_c +)
|
|
FF rd[0]
|
|
|
|
Delay: 11.869ns (24.7% logic, 75.3% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.869ns physical path delay SLICE_59 to SLICE_122 meets
|
|
40.000ns delay constraint less
|
|
0.037ns skew and
|
|
0.282ns CE_SET requirement (totaling 39.681ns) by 27.812ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_59 to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R18C21A.CLK to R18C21A.Q1 SLICE_59 (from sys_clock_c)
|
|
ROUTE 2 1.427 R18C21A.Q1 to R19C21C.B1 flash_count[8]
|
|
CTOF_DEL --- 0.495 R19C21C.B1 to R19C21C.F1 SLICE_120
|
|
ROUTE 1 0.967 R19C21C.F1 to R19C21C.A0 un1_flash_countlto13_1
|
|
CTOF_DEL --- 0.495 R19C21C.A0 to R19C21C.F0 SLICE_120
|
|
ROUTE 1 0.315 R19C21C.F0 to R19C21A.D1 un1_flash_countlt14
|
|
CTOF_DEL --- 0.495 R19C21A.D1 to R19C21A.F1 SLICE_156
|
|
ROUTE 1 1.088 R19C21A.F1 to R21C21B.B1 un1_flash_countlt21
|
|
CTOF_DEL --- 0.495 R21C21B.B1 to R21C21B.F1 SLICE_122
|
|
ROUTE 19 3.547 R21C21B.F1 to R21C26D.C1 un1_flash_countlt22
|
|
CTOF_DEL --- 0.495 R21C26D.C1 to R21C26D.F1 SLICE_94
|
|
ROUTE 4 1.598 R21C26D.F1 to R21C21B.CE un1_flash_count_1 (to sys_clock_c)
|
|
--------
|
|
11.869 (24.7% logic, 75.3% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_59:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.560 126.PADDI to R18C21A.CLK sys_clock_c
|
|
--------
|
|
2.560 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_122:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 2.523 126.PADDI to R21C21B.CLK sys_clock_c
|
|
--------
|
|
2.523 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Report: 31.490MHz is the maximum frequency for this preference.
|
|
|
|
|
|
================================================================================
|
|
Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
|
899 items scored, 175 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.607ns (weighted slack = -67.249ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[1] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D8/count[3] (to circuit_clk +)
|
|
FF apple_module/D8/count[2]
|
|
|
|
Delay: 8.689ns (39.4% logic, 60.6% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.689ns physical path delay apple_module/SLICE_100 to apple_module/D8/SLICE_79 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.636ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.918ns) by 9.607ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_100 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q1 apple_module/SLICE_100 (from apple_module/C5/y1)
|
|
ROUTE 4 0.765 R21C30C.Q1 to R21C31A.C1 apple_module/char_ready
|
|
CTOF_DEL --- 0.495 R21C31A.C1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 1.060 R21C33A.F1 to R19C33B.D1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R19C33B.D1 to R19C33B.F1 apple_module/SLICE_141
|
|
ROUTE 2 0.662 R19C33B.F1 to R19C33D.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
|
|
--------
|
|
8.689 (39.4% logic, 60.6% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.607ns (weighted slack = -67.249ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[1] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D8/count[1] (to circuit_clk +)
|
|
FF apple_module/D8/count[0]
|
|
|
|
Delay: 8.689ns (39.4% logic, 60.6% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.689ns physical path delay apple_module/SLICE_100 to apple_module/D8/SLICE_78 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.636ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.918ns) by 9.607ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_100 to apple_module/D8/SLICE_78:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q1 apple_module/SLICE_100 (from apple_module/C5/y1)
|
|
ROUTE 4 0.765 R21C30C.Q1 to R21C31A.C1 apple_module/char_ready
|
|
CTOF_DEL --- 0.495 R21C31A.C1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 1.060 R21C33A.F1 to R19C33B.D1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R19C33B.D1 to R19C33B.F1 apple_module/SLICE_141
|
|
ROUTE 2 0.662 R19C33B.F1 to R19C33A.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
|
|
--------
|
|
8.689 (39.4% logic, 60.6% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D8/SLICE_78:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33A.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.382ns (weighted slack = -65.674ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[1] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D9/count[3] (to circuit_clk +)
|
|
FF apple_module/D9/count[2]
|
|
|
|
Delay: 8.427ns (40.6% logic, 59.4% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.427ns physical path delay apple_module/SLICE_100 to apple_module/D9/SLICE_81 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.673ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.955ns) by 9.382ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_100 to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q1 apple_module/SLICE_100 (from apple_module/C5/y1)
|
|
ROUTE 4 0.765 R21C30C.Q1 to R21C31A.C1 apple_module/char_ready
|
|
CTOF_DEL --- 0.495 R21C31A.C1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 0.798 R21C33A.F1 to R21C32A.C1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R21C32A.C1 to R21C32A.F1 apple_module/SLICE_87
|
|
ROUTE 2 0.662 R21C32A.F1 to R21C32C.CE apple_module/D9/count_cnv_1[0] (to circuit_clk)
|
|
--------
|
|
8.427 (40.6% logic, 59.4% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.861 RPLL.CLKOS to R21C32C.CLK circuit_clk
|
|
--------
|
|
3.783 (29.9% logic, 70.1% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.382ns (weighted slack = -65.674ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[1] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D9/count[1] (to circuit_clk +)
|
|
FF apple_module/D9/count[0]
|
|
|
|
Delay: 8.427ns (40.6% logic, 59.4% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.427ns physical path delay apple_module/SLICE_100 to apple_module/D9/SLICE_80 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.673ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.955ns) by 9.382ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_100 to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q1 apple_module/SLICE_100 (from apple_module/C5/y1)
|
|
ROUTE 4 0.765 R21C30C.Q1 to R21C31A.C1 apple_module/char_ready
|
|
CTOF_DEL --- 0.495 R21C31A.C1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 0.798 R21C33A.F1 to R21C32A.C1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R21C32A.C1 to R21C32A.F1 apple_module/SLICE_87
|
|
ROUTE 2 0.662 R21C32A.F1 to R21C32D.CE apple_module/D9/count_cnv_1[0] (to circuit_clk)
|
|
--------
|
|
8.427 (40.6% logic, 59.4% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.861 RPLL.CLKOS to R21C32D.CLK circuit_clk
|
|
--------
|
|
3.783 (29.9% logic, 70.1% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.270ns (weighted slack = -64.890ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[5] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D8/count[3] (to circuit_clk +)
|
|
FF apple_module/D8/count[2]
|
|
|
|
Delay: 8.352ns (35.0% logic, 65.0% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.352ns physical path delay apple_module/SLICE_93 to apple_module/D8/SLICE_79 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.636ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.918ns) by 9.270ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_93 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C33D.CLK to R21C33D.Q0 apple_module/SLICE_93 (from apple_module/C5/y1)
|
|
ROUTE 2 1.625 R21C33D.Q0 to R21C31C.C0 apple_module/wc2_i
|
|
CTOF_DEL --- 0.495 R21C31C.C0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 1.060 R21C33A.F1 to R19C33B.D1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R19C33B.D1 to R19C33B.F1 apple_module/SLICE_141
|
|
ROUTE 2 0.662 R19C33B.F1 to R19C33D.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
|
|
--------
|
|
8.352 (35.0% logic, 65.0% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C33D.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.270ns (weighted slack = -64.890ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[5] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D8/count[1] (to circuit_clk +)
|
|
FF apple_module/D8/count[0]
|
|
|
|
Delay: 8.352ns (35.0% logic, 65.0% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.352ns physical path delay apple_module/SLICE_93 to apple_module/D8/SLICE_78 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.636ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.918ns) by 9.270ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_93 to apple_module/D8/SLICE_78:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C33D.CLK to R21C33D.Q0 apple_module/SLICE_93 (from apple_module/C5/y1)
|
|
ROUTE 2 1.625 R21C33D.Q0 to R21C31C.C0 apple_module/wc2_i
|
|
CTOF_DEL --- 0.495 R21C31C.C0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 1.060 R21C33A.F1 to R19C33B.D1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R19C33B.D1 to R19C33B.F1 apple_module/SLICE_141
|
|
ROUTE 2 0.662 R19C33B.F1 to R19C33A.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
|
|
--------
|
|
8.352 (35.0% logic, 65.0% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C33D.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D8/SLICE_78:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33A.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.045ns (weighted slack = -63.315ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[5] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D9/count[3] (to circuit_clk +)
|
|
FF apple_module/D9/count[2]
|
|
|
|
Delay: 8.090ns (36.2% logic, 63.8% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.090ns physical path delay apple_module/SLICE_93 to apple_module/D9/SLICE_81 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.673ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.955ns) by 9.045ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_93 to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C33D.CLK to R21C33D.Q0 apple_module/SLICE_93 (from apple_module/C5/y1)
|
|
ROUTE 2 1.625 R21C33D.Q0 to R21C31C.C0 apple_module/wc2_i
|
|
CTOF_DEL --- 0.495 R21C31C.C0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 0.798 R21C33A.F1 to R21C32A.C1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R21C32A.C1 to R21C32A.F1 apple_module/SLICE_87
|
|
ROUTE 2 0.662 R21C32A.F1 to R21C32C.CE apple_module/D9/count_cnv_1[0] (to circuit_clk)
|
|
--------
|
|
8.090 (36.2% logic, 63.8% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C33D.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.861 RPLL.CLKOS to R21C32C.CLK circuit_clk
|
|
--------
|
|
3.783 (29.9% logic, 70.1% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 9.045ns (weighted slack = -63.315ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[5] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D9/count[1] (to circuit_clk +)
|
|
FF apple_module/D9/count[0]
|
|
|
|
Delay: 8.090ns (36.2% logic, 63.8% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.090ns physical path delay apple_module/SLICE_93 to apple_module/D9/SLICE_80 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.673ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.955ns) by 9.045ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_93 to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C33D.CLK to R21C33D.Q0 apple_module/SLICE_93 (from apple_module/C5/y1)
|
|
ROUTE 2 1.625 R21C33D.Q0 to R21C31C.C0 apple_module/wc2_i
|
|
CTOF_DEL --- 0.495 R21C31C.C0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.983 R21C31C.F0 to R21C33D.D1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.D1 to R21C33D.F1 apple_module/SLICE_93
|
|
ROUTE 1 0.436 R21C33D.F1 to R21C33D.C0 apple_module/un6_y1
|
|
CTOF_DEL --- 0.495 R21C33D.C0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 0.798 R21C33A.F1 to R21C32A.C1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R21C32A.C1 to R21C32A.F1 apple_module/SLICE_87
|
|
ROUTE 2 0.662 R21C32A.F1 to R21C32D.CE apple_module/D9/count_cnv_1[0] (to circuit_clk)
|
|
--------
|
|
8.090 (36.2% logic, 63.8% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C33D.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.861 RPLL.CLKOS to R21C32D.CLK circuit_clk
|
|
--------
|
|
3.783 (29.9% logic, 70.1% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 8.704ns (weighted slack = -60.928ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[1] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D8/count[3] (to circuit_clk +)
|
|
FF apple_module/D8/count[2]
|
|
|
|
Delay: 7.786ns (37.6% logic, 62.4% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.786ns physical path delay apple_module/SLICE_100 to apple_module/D8/SLICE_79 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.636ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.918ns) by 8.704ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_100 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q1 apple_module/SLICE_100 (from apple_module/C5/y1)
|
|
ROUTE 4 0.765 R21C30C.Q1 to R21C31A.C1 apple_module/char_ready
|
|
CTOF_DEL --- 0.495 R21C31A.C1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 1.011 R21C31C.F0 to R21C33D.A0 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.A0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 1.060 R21C33A.F1 to R19C33B.D1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R19C33B.D1 to R19C33B.F1 apple_module/SLICE_141
|
|
ROUTE 2 0.662 R19C33B.F1 to R19C33D.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
|
|
--------
|
|
7.786 (37.6% logic, 62.4% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 8.704ns (weighted slack = -60.928ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C7/states[1] (from apple_module/C5/y1 -)
|
|
Destination: FF Data in apple_module/D8/count[1] (to circuit_clk +)
|
|
FF apple_module/D8/count[0]
|
|
|
|
Delay: 7.786ns (37.6% logic, 62.4% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.786ns physical path delay apple_module/SLICE_100 to apple_module/D8/SLICE_78 exceeds
|
|
(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
|
|
10.000ns delay constraint less
|
|
10.636ns skew and
|
|
0.000ns feedback compensation and
|
|
0.282ns CE_SET requirement (totaling -0.918ns) by 8.704ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_100 to apple_module/D8/SLICE_78:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C30C.CLK to R21C30C.Q1 apple_module/SLICE_100 (from apple_module/C5/y1)
|
|
ROUTE 4 0.765 R21C30C.Q1 to R21C31A.C1 apple_module/char_ready
|
|
CTOF_DEL --- 0.495 R21C31A.C1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 1.011 R21C31C.F0 to R21C33D.A0 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C33D.A0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.659 R21C33D.F0 to R21C33A.D1 apple_module/wc1_i
|
|
CTOF_DEL --- 0.495 R21C33A.D1 to R21C33A.F1 apple_module/SLICE_152
|
|
ROUTE 5 1.060 R21C33A.F1 to R19C33B.D1 apple_module/load_v_i_0
|
|
CTOF_DEL --- 0.495 R19C33B.D1 to R19C33B.F1 apple_module/SLICE_141
|
|
ROUTE 2 0.662 R19C33B.F1 to R19C33A.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
|
|
--------
|
|
7.786 (37.6% logic, 62.4% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.770 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
14.456 (17.8% logic, 82.2% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/D8/SLICE_78:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33A.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Warning: 7.286MHz is the maximum frequency for this preference.
|
|
|
|
|
|
================================================================================
|
|
Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
|
1120 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 5.355ns (weighted slack = 21.420ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D7/count[3] (from circuit_clk +)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 7.840ns (31.0% logic, 69.0% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.840ns physical path delay apple_module/D7/SLICE_86 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
10.000ns delay constraint less
|
|
-3.144ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 13.195ns) by 5.355ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D7/SLICE_86 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86 (from circuit_clk)
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.040 R21C32B.F1 to R21C31C.B1 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R21C31C.B1 to R21C31C.F1 apple_module/SLICE_77
|
|
ROUTE 8 0.680 R21C31C.F1 to R21C30D.D1 apple_module/clr
|
|
CTOF_DEL --- 0.495 R21C30D.D1 to R21C30D.F1 apple_module/SLICE_117
|
|
ROUTE 1 1.004 R21C30D.F1 to R21C30B.B1 apple_module/msb
|
|
CTOF_DEL --- 0.495 R21C30B.B1 to R21C30B.F1 apple_module/SLICE_128
|
|
ROUTE 1 1.174 R21C30B.F1 to *R_R20C27.DIA5 apple_module/C3/input[5] (to apple_module/D10/y1)
|
|
--------
|
|
7.840 (31.0% logic, 69.0% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D7/SLICE_86:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 21.692ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: DP8KC Port apple_module/D14a/sram_1_0_0_0(ASIC) (from apple_module/C5/y1 -)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 10.657ns (56.0% logic, 44.0% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
10.657ns physical path delay apple_module/D14a/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
40.000ns delay constraint less
|
|
7.702ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 32.349ns) by 21.692ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D14a/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2Q_DEL --- 4.979 *R_R13C24.CLKA to *R_R13C24.DOA0 apple_module/D14a/sram_1_0_0_0 (from apple_module/C5/y1)
|
|
ROUTE 1 2.438 *R_R13C24.DOA0 to R21C29A.D0 apple_module/buffer_char_out_4[0]
|
|
CTOF_DEL --- 0.495 R21C29A.D0 to R21C29A.F0 apple_module/SLICE_129
|
|
ROUTE 1 1.004 R21C29A.F0 to R21C29A.B1 apple_module/un1_a_3[0]
|
|
CTOF_DEL --- 0.495 R21C29A.B1 to R21C29A.F1 apple_module/SLICE_129
|
|
ROUTE 1 1.246 R21C29A.F1 to *R_R20C27.DIA4 apple_module/C3/input[4] (to apple_module/D10/y1)
|
|
--------
|
|
10.657 (56.0% logic, 44.0% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D14a/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.980 R2C19D.F0 to *R_R13C24.CLKA apple_module/C5/y1
|
|
--------
|
|
14.666 (17.6% logic, 82.4% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 21.841ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: DP8KC Port apple_module/D4a/sram_1_0_0_0(ASIC) (from apple_module/C5/y1 -)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 10.508ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
10.508ns physical path delay apple_module/D4a/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
40.000ns delay constraint less
|
|
7.702ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 32.349ns) by 21.841ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D4a/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2Q_DEL --- 4.979 *R_R20C36.CLKA to *R_R20C36.DOA0 apple_module/D4a/sram_1_0_0_0 (from apple_module/C5/y1)
|
|
ROUTE 1 2.292 *R_R20C36.DOA0 to R21C31B.B0 apple_module/buffer_char_out_2[0]
|
|
CTOF_DEL --- 0.495 R21C31B.B0 to R21C31B.F0 apple_module/SLICE_131
|
|
ROUTE 1 0.436 R21C31B.F0 to R21C31B.C1 apple_module/un1_a_1[0]
|
|
CTOF_DEL --- 0.495 R21C31B.C1 to R21C31B.F1 apple_module/SLICE_131
|
|
ROUTE 1 1.811 R21C31B.F1 to *R_R20C27.DIA2 apple_module/C3/input[2] (to apple_module/D10/y1)
|
|
--------
|
|
10.508 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D4a/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.980 R2C19D.F0 to *R_R20C36.CLKA apple_module/C5/y1
|
|
--------
|
|
14.666 (17.6% logic, 82.4% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 21.907ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: DP8KC Port apple_module/D5b/sram_1_0_0_0(ASIC) (from apple_module/C5/y1 -)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 10.442ns (57.2% logic, 42.8% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
10.442ns physical path delay apple_module/D5b/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
40.000ns delay constraint less
|
|
7.702ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 32.349ns) by 21.907ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D5b/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2Q_DEL --- 4.979 *R_R20C21.CLKA to *R_R20C21.DOA0 apple_module/D5b/sram_1_0_0_0 (from apple_module/C5/y1)
|
|
ROUTE 1 2.673 *R_R20C21.DOA0 to R21C29C.A0 apple_module/buffer_char_out_1[0]
|
|
CTOF_DEL --- 0.495 R21C29C.A0 to R21C29C.F0 apple_module/SLICE_132
|
|
ROUTE 1 0.626 R21C29C.F0 to R21C29C.D1 apple_module/un1_a_2[0]
|
|
CTOF_DEL --- 0.495 R21C29C.D1 to R21C29C.F1 apple_module/SLICE_132
|
|
ROUTE 1 1.174 R21C29C.F1 to *R_R20C27.DIA1 apple_module/C3/input[1] (to apple_module/D10/y1)
|
|
--------
|
|
10.442 (57.2% logic, 42.8% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D5b/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.980 R2C19D.F0 to *R_R20C21.CLKA apple_module/C5/y1
|
|
--------
|
|
14.666 (17.6% logic, 82.4% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 22.155ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: DP8KC Port apple_module/D4b/sram_1_0_0_0(ASIC) (from apple_module/C5/y1 -)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 10.194ns (58.6% logic, 41.4% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
10.194ns physical path delay apple_module/D4b/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
40.000ns delay constraint less
|
|
7.702ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 32.349ns) by 22.155ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D4b/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2Q_DEL --- 4.979 *R_R20C33.CLKA to *R_R20C33.DOA0 apple_module/D4b/sram_1_0_0_0 (from apple_module/C5/y1)
|
|
ROUTE 1 2.011 *R_R20C33.DOA0 to R21C30A.C0 apple_module/buffer_char_out_3[0]
|
|
CTOF_DEL --- 0.495 R21C30A.C0 to R21C30A.F0 apple_module/SLICE_130
|
|
ROUTE 1 0.656 R21C30A.F0 to R21C30A.A1 apple_module/un1_a[0]
|
|
CTOF_DEL --- 0.495 R21C30A.A1 to R21C30A.F1 apple_module/SLICE_130
|
|
ROUTE 1 1.558 R21C30A.F1 to *R_R20C27.DIA3 apple_module/C3/input[3] (to apple_module/D10/y1)
|
|
--------
|
|
10.194 (58.6% logic, 41.4% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D4b/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.980 R2C19D.F0 to *R_R20C33.CLKA apple_module/C5/y1
|
|
--------
|
|
14.666 (17.6% logic, 82.4% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 22.288ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: DP8KC Port apple_module/D5a/sram_1_0_0_0(ASIC) (from apple_module/C5/y1 -)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 10.061ns (59.3% logic, 40.7% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
10.061ns physical path delay apple_module/D5a/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
40.000ns delay constraint less
|
|
7.702ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 32.349ns) by 22.288ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D5a/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2Q_DEL --- 4.979 *R_R13C21.CLKA to *R_R13C21.DOA0 apple_module/D5a/sram_1_0_0_0 (from apple_module/C5/y1)
|
|
ROUTE 1 2.807 *R_R13C21.DOA0 to R21C29B.B0 apple_module/buffer_char_out_0[0]
|
|
CTOF_DEL --- 0.495 R21C29B.B0 to R21C29B.F0 apple_module/SLICE_133
|
|
ROUTE 1 0.436 R21C29B.F0 to R21C29B.C1 apple_module/un1_a_3_0[0]
|
|
CTOF_DEL --- 0.495 R21C29B.C1 to R21C29B.F1 apple_module/SLICE_133
|
|
ROUTE 1 0.849 R21C29B.F1 to *R_R20C27.DIA0 apple_module/C3/input[0] (to apple_module/D10/y1)
|
|
--------
|
|
10.061 (59.3% logic, 40.7% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D5a/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.980 R2C19D.F0 to *R_R13C21.CLKA apple_module/C5/y1
|
|
--------
|
|
14.666 (17.6% logic, 82.4% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 22.436ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: DP8KC Port apple_module/D14b/sram_1_0_0_0(ASIC) (from apple_module/C5/y1 -)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 9.913ns (60.2% logic, 39.8% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
9.913ns physical path delay apple_module/D14b/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
40.000ns delay constraint less
|
|
7.702ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 32.349ns) by 22.436ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D14b/sram_1_0_0_0 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2Q_DEL --- 4.979 *R_R13C27.CLKA to *R_R13C27.DOA0 apple_module/D14b/sram_1_0_0_0 (from apple_module/C5/y1)
|
|
ROUTE 1 2.144 *R_R13C27.DOA0 to R21C30B.C0 apple_module/buffer_char_out_5[0]
|
|
CTOF_DEL --- 0.495 R21C30B.C0 to R21C30B.F0 apple_module/SLICE_128
|
|
ROUTE 1 0.626 R21C30B.F0 to R21C30B.D1 apple_module/buffer_char_in[5]
|
|
CTOF_DEL --- 0.495 R21C30B.D1 to R21C30B.F1 apple_module/SLICE_128
|
|
ROUTE 1 1.174 R21C30B.F1 to *R_R20C27.DIA5 apple_module/C3/input[5] (to apple_module/D10/y1)
|
|
--------
|
|
9.913 (60.2% logic, 39.8% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D14b/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 1.510 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 3.914 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.495 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 3.980 R2C19D.F0 to *R_R13C27.CLKA apple_module/C5/y1
|
|
--------
|
|
14.666 (17.6% logic, 82.4% route), 5 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 5.639ns (weighted slack = 22.556ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C13/states[3] (from circuit_clk +)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 7.593ns (38.5% logic, 61.5% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.593ns physical path delay apple_module/SLICE_90 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
10.000ns delay constraint less
|
|
-3.181ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 13.232ns) by 5.639ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_90 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R21C31A.CLK to R21C31A.Q1 apple_module/SLICE_90 (from circuit_clk)
|
|
ROUTE 5 0.645 R21C31A.Q1 to R21C31A.D1 apple_module/states[3]
|
|
CTOF_DEL --- 0.495 R21C31A.D1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.702 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.495 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.461 R21C31C.F0 to R21C31C.C1 apple_module/clear_char
|
|
CTOF_DEL --- 0.495 R21C31C.C1 to R21C31C.F1 apple_module/SLICE_77
|
|
ROUTE 8 0.680 R21C31C.F1 to R21C30D.D1 apple_module/clr
|
|
CTOF_DEL --- 0.495 R21C30D.D1 to R21C30D.F1 apple_module/SLICE_117
|
|
ROUTE 1 1.004 R21C30D.F1 to R21C30B.B1 apple_module/msb
|
|
CTOF_DEL --- 0.495 R21C30B.B1 to R21C30B.F1 apple_module/SLICE_128
|
|
ROUTE 1 1.174 R21C30B.F1 to *R_R20C27.DIA5 apple_module/C3/input[5] (to apple_module/D10/y1)
|
|
--------
|
|
7.593 (38.5% logic, 61.5% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.861 RPLL.CLKOS to R21C31A.CLK circuit_clk
|
|
--------
|
|
3.783 (29.9% logic, 70.1% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 5.644ns (weighted slack = 22.576ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D7/count[3] (from circuit_clk +)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 7.551ns (19.1% logic, 80.9% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.551ns physical path delay apple_module/D7/SLICE_86 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
10.000ns delay constraint less
|
|
-3.144ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 13.195ns) by 5.644ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D7/SLICE_86 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86 (from circuit_clk)
|
|
ROUTE 12 1.388 R17C33B.Q0 to R18C32A.B0 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.495 R18C32A.B0 to R18C32A.F0 apple_module/SLICE_125
|
|
ROUTE 8 2.910 R18C32A.F0 to R21C31B.A1 apple_module/y2_0
|
|
CTOF_DEL --- 0.495 R21C31B.A1 to R21C31B.F1 apple_module/SLICE_131
|
|
ROUTE 1 1.811 R21C31B.F1 to *R_R20C27.DIA2 apple_module/C3/input[2] (to apple_module/D10/y1)
|
|
--------
|
|
7.551 (19.1% logic, 80.9% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D7/SLICE_86:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 5.687ns (weighted slack = 22.748ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D8/count[2] (from circuit_clk +)
|
|
Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
|
|
|
|
Delay: 7.508ns (19.2% logic, 80.8% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.508ns physical path delay apple_module/D8/SLICE_79 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
10.000ns delay constraint less
|
|
-3.144ns skew and
|
|
0.000ns feedback compensation and
|
|
-0.051ns DATA_SET requirement (totaling 13.195ns) by 5.687ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D8/SLICE_79 to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R19C33D.CLK to R19C33D.Q0 apple_module/D8/SLICE_79 (from circuit_clk)
|
|
ROUTE 6 1.345 R19C33D.Q0 to R18C32A.A0 apple_module/count[2]
|
|
CTOF_DEL --- 0.495 R18C32A.A0 to R18C32A.F0 apple_module/SLICE_125
|
|
ROUTE 8 2.910 R18C32A.F0 to R21C31B.A1 apple_module/y2_0
|
|
CTOF_DEL --- 0.495 R21C31B.A1 to R21C31B.F1 apple_module/SLICE_131
|
|
ROUTE 1 1.811 R21C31B.F1 to *R_R20C27.DIA2 apple_module/C3/input[2] (to apple_module/D10/y1)
|
|
--------
|
|
7.508 (19.2% logic, 80.8% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
3.820 (29.6% logic, 70.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C3/LineBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.132 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.790 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 1.898 RPLL.CLKOS to R18C32C.CLK circuit_clk
|
|
REG_DEL --- 0.452 R18C32C.CLK to R18C32C.Q0 apple_module/D11/SLICE_75
|
|
ROUTE 6 0.648 R18C32C.Q0 to R18C31D.D1 apple_module/char_column[2]
|
|
CTOF_DEL --- 0.495 R18C31D.D1 to R18C31D.F1 apple_module/SLICE_82
|
|
ROUTE 4 1.549 R18C31D.F1 to *R_R20C27.CLKA apple_module/D10/y1
|
|
--------
|
|
6.964 (29.9% logic, 70.1% route), 4 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Report: 53.821MHz is the maximum frequency for this preference.
|
|
|
|
Report Summary
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY NET "sys_clock_c" 25.000000 | | |
|
|
MHz ; | 25.000 MHz| 31.490 MHz| 2
|
|
| | |
|
|
FREQUENCY NET "circuit_clk" 14.285714 | | |
|
|
MHz ; | 14.286 MHz| 7.286 MHz| 7 *
|
|
| | |
|
|
FREQUENCY PORT "sys_clock" 25.000000 | | |
|
|
MHz ; | 25.000 MHz| 53.821 MHz| 5
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
1 preference(marked by "*" above) not met.
|
|
|
|
----------------------------------------------------------------------------
|
|
Critical Nets | Loads| Errors| % of total
|
|
----------------------------------------------------------------------------
|
|
apple_module/wc1_i | 5| 168| 96.00%
|
|
| | |
|
|
apple_module/clear_char | 4| 117| 66.86%
|
|
| | |
|
|
apple_module/un6_y1 | 1| 78| 44.57%
|
|
| | |
|
|
apple_module/load_v_i_0 | 5| 69| 39.43%
|
|
| | |
|
|
apple_module/char_ready | 4| 57| 32.57%
|
|
| | |
|
|
apple_module/y2_1 | 2| 38| 21.71%
|
|
| | |
|
|
apple_module/cleared_last | 1| 37| 21.14%
|
|
| | |
|
|
apple_module/wc2_i | 2| 37| 21.14%
|
|
| | |
|
|
apple_module/D8/N_19 | 4| 36| 20.57%
|
|
| | |
|
|
apple_module/count_5[0] | 4| 36| 20.57%
|
|
| | |
|
|
apple_module/D9/N_19 | 3| 27| 15.43%
|
|
| | |
|
|
apple_module/D8/count_cnv_0[0] | 2| 22| 12.57%
|
|
| | |
|
|
apple_module/D9/count_cnv_1[0] | 2| 20| 11.43%
|
|
| | |
|
|
apple_module/D8/count_n2 | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/D8/count_n1 | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/D8/N_46 | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/D8/count_n3 | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/D9/count_n1 | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/D9/N_45 | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/screen_clear_inhibit | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/line_clear_inhibit | 1| 18| 10.29%
|
|
| | |
|
|
apple_module/write_i | 8| 18| 10.29%
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
Clock Domains Analysis
|
|
------------------------
|
|
|
|
Found 7 clocks:
|
|
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
|
|
|
|
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 18
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
|
|
|
|
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 24
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 9
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 7
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 38
|
|
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ; Transfers: 1
|
|
|
|
|
|
Timing summary (Setup):
|
|
---------------
|
|
|
|
Timing errors: 175 Score: 8347444
|
|
Cumulative negative slack: 8347444
|
|
|
|
Constraints cover 3276 paths, 9 nets, and 1223 connections (98.47% coverage)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.2.115
|
|
Thu Aug 08 18:39:39 2019
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
Report Information
|
|
------------------
|
|
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Apple1Display_impl1.twr -gui -msgset C:/Dev/Apple1Display/promote.xml Apple1Display_impl1.ncd Apple1Display_impl1.prf
|
|
Design file: apple1display_impl1.ncd
|
|
Preference file: apple1display_impl1.prf
|
|
Device,speed: LCMXO2-7000HC,m
|
|
Report level: verbose report, limited to 10 items per preference
|
|
--------------------------------------------------------------------------------
|
|
|
|
BLOCK ASYNCPATHS
|
|
BLOCK RESETPATHS
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
================================================================================
|
|
Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
|
|
1257 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[21] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[21] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_52 to SLICE_52 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_52 to SLICE_52:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22D.CLK to R18C22D.Q0 SLICE_52 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22D.Q0 to R18C22D.A0 flash_count[21]
|
|
CTOF_DEL --- 0.101 R18C22D.A0 to R18C22D.F0 SLICE_52
|
|
ROUTE 1 0.000 R18C22D.F0 to R18C22D.DI0 un6_flash_count[11] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_52:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22D.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_52:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22D.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[19] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[19] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_53 to SLICE_53 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_53 to SLICE_53:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22C.CLK to R18C22C.Q0 SLICE_53 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22C.Q0 to R18C22C.A0 flash_count[19]
|
|
CTOF_DEL --- 0.101 R18C22C.A0 to R18C22C.F0 SLICE_53
|
|
ROUTE 1 0.000 R18C22C.F0 to R18C22C.DI0 un6_flash_count[13] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_53:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22C.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_53:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22C.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[20] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[20] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_53 to SLICE_53 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_53 to SLICE_53:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22C.CLK to R18C22C.Q1 SLICE_53 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22C.Q1 to R18C22C.A1 flash_count[20]
|
|
CTOF_DEL --- 0.101 R18C22C.A1 to R18C22C.F1 SLICE_53
|
|
ROUTE 1 0.000 R18C22C.F1 to R18C22C.DI1 un6_flash_count[12] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_53:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22C.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_53:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22C.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[18] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[18] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_54 to SLICE_54 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_54 to SLICE_54:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22B.CLK to R18C22B.Q1 SLICE_54 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22B.Q1 to R18C22B.A1 flash_count[18]
|
|
CTOF_DEL --- 0.101 R18C22B.A1 to R18C22B.F1 SLICE_54
|
|
ROUTE 1 0.000 R18C22B.F1 to R18C22B.DI1 un6_flash_count[14] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_54:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22B.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_54:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22B.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[17] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[17] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_54 to SLICE_54 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_54 to SLICE_54:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22B.CLK to R18C22B.Q0 SLICE_54 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22B.Q0 to R18C22B.A0 flash_count[17]
|
|
CTOF_DEL --- 0.101 R18C22B.A0 to R18C22B.F0 SLICE_54
|
|
ROUTE 1 0.000 R18C22B.F0 to R18C22B.DI0 un6_flash_count[15] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_54:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22B.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_54:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22B.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[16] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[16] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_55 to SLICE_55 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_55 to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22A.CLK to R18C22A.Q1 SLICE_55 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22A.Q1 to R18C22A.A1 flash_count[16]
|
|
CTOF_DEL --- 0.101 R18C22A.A1 to R18C22A.F1 SLICE_55
|
|
ROUTE 1 0.000 R18C22A.F1 to R18C22A.DI1 un6_flash_count[16] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22A.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22A.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[15] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[15] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_55 to SLICE_55 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_55 to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C22A.CLK to R18C22A.Q0 SLICE_55 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C22A.Q0 to R18C22A.A0 flash_count[15]
|
|
CTOF_DEL --- 0.101 R18C22A.A0 to R18C22A.F0 SLICE_55
|
|
ROUTE 1 0.000 R18C22A.F0 to R18C22A.DI0 un6_flash_count[17] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22A.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C22A.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[14] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[14] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_56 to SLICE_56 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_56 to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C21D.CLK to R18C21D.Q1 SLICE_56 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C21D.Q1 to R18C21D.A1 flash_count[14]
|
|
CTOF_DEL --- 0.101 R18C21D.A1 to R18C21D.F1 SLICE_56
|
|
ROUTE 1 0.000 R18C21D.F1 to R18C21D.DI1 un6_flash_count[18] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C21D.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C21D.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[13] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[13] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_56 to SLICE_56 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_56 to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C21D.CLK to R18C21D.Q0 SLICE_56 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C21D.Q0 to R18C21D.A0 flash_count[13]
|
|
CTOF_DEL --- 0.101 R18C21D.A0 to R18C21D.F0 SLICE_56
|
|
ROUTE 1 0.000 R18C21D.F0 to R18C21D.DI0 un6_flash_count[19] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C21D.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C21D.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q flash_count[11] (from sys_clock_c +)
|
|
Destination: FF Data in flash_count[11] (to sys_clock_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay SLICE_57 to SLICE_57 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_57 to SLICE_57:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C21C.CLK to R18C21C.Q0 SLICE_57 (from sys_clock_c)
|
|
ROUTE 2 0.132 R18C21C.Q0 to R18C21C.A0 flash_count[11]
|
|
CTOF_DEL --- 0.101 R18C21C.A0 to R18C21C.F0 SLICE_57
|
|
ROUTE 1 0.000 R18C21C.F0 to R18C21C.DI0 un6_flash_count[21] (to sys_clock_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to SLICE_57:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C21C.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path sys_clock to SLICE_57:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 38 0.907 126.PADDI to R18C21C.CLK sys_clock_c
|
|
--------
|
|
0.907 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
================================================================================
|
|
Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
|
899 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D6/count[1] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D6/count[1] (to circuit_clk +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay apple_module/D6/SLICE_72 to apple_module/D6/SLICE_72 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D6/SLICE_72 to apple_module/D6/SLICE_72:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C33C.CLK to R18C33C.Q0 apple_module/D6/SLICE_72 (from circuit_clk)
|
|
ROUTE 4 0.132 R18C33C.Q0 to R18C33C.A0 apple_module/D6/count[1]
|
|
CTOF_DEL --- 0.101 R18C33C.A0 to R18C33C.F0 apple_module/D6/SLICE_72
|
|
ROUTE 1 0.000 R18C33C.F0 to R18C33C.DI0 apple_module/D6/count_n1 (to circuit_clk)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D6/SLICE_72:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C33C.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D6/SLICE_72:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C33C.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D15/count[2] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D15/count[2] (to circuit_clk +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay apple_module/D15/SLICE_71 to apple_module/D15/SLICE_71 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D15/SLICE_71 to apple_module/D15/SLICE_71:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R17C32B.CLK to R17C32B.Q1 apple_module/D15/SLICE_71 (from circuit_clk)
|
|
ROUTE 2 0.132 R17C32B.Q1 to R17C32B.A1 apple_module/D15/count[2]
|
|
CTOF_DEL --- 0.101 R17C32B.A1 to R17C32B.F1 apple_module/D15/SLICE_71
|
|
ROUTE 1 0.000 R17C32B.F1 to R17C32B.DI1 apple_module/D15/N_42_i (to circuit_clk)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D15/SLICE_71:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C32B.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D15/SLICE_71:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C32B.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D11/count_0[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D11/count_0[3] (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/SLICE_82 to apple_module/SLICE_82 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_82 to apple_module/SLICE_82:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C31D.CLK to R18C31D.Q0 apple_module/SLICE_82 (from circuit_clk)
|
|
ROUTE 10 0.133 R18C31D.Q0 to R18C31D.A0 apple_module/count_i[3]
|
|
CTOF_DEL --- 0.101 R18C31D.A0 to R18C31D.F0 apple_module/SLICE_82
|
|
ROUTE 1 0.000 R18C31D.F0 to R18C31D.DI0 apple_module/D11/count_5_0_0[3] (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/SLICE_82:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C31D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/SLICE_82:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C31D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D9/count[2] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D9/count[2] (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D9/SLICE_81 to apple_module/D9/SLICE_81 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D9/SLICE_81 to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C32C.CLK to R21C32C.Q0 apple_module/D9/SLICE_81 (from circuit_clk)
|
|
ROUTE 5 0.133 R21C32C.Q0 to R21C32C.A0 apple_module/count_0[2]
|
|
CTOF_DEL --- 0.101 R21C32C.A0 to R21C32C.F0 apple_module/D9/SLICE_81
|
|
ROUTE 1 0.000 R21C32C.F0 to R21C32C.DI0 apple_module/D9/N_44_i (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32C.CLK circuit_clk
|
|
--------
|
|
0.689 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32C.CLK circuit_clk
|
|
--------
|
|
0.689 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D9/count[1] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D9/count[1] (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D9/SLICE_80 to apple_module/D9/SLICE_80 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D9/SLICE_80 to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C32D.CLK to R21C32D.Q1 apple_module/D9/SLICE_80 (from circuit_clk)
|
|
ROUTE 4 0.133 R21C32D.Q1 to R21C32D.A1 apple_module/count_0[1]
|
|
CTOF_DEL --- 0.101 R21C32D.A1 to R21C32D.F1 apple_module/D9/SLICE_80
|
|
ROUTE 1 0.000 R21C32D.F1 to R21C32D.DI1 apple_module/D9/count_n1 (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32D.CLK circuit_clk
|
|
--------
|
|
0.689 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32D.CLK circuit_clk
|
|
--------
|
|
0.689 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D1/Qe (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D1/Qf (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D1/SLICE_65 to apple_module/D1/SLICE_66 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D1/SLICE_65 to apple_module/D1/SLICE_66:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R19C31D.CLK to R19C31D.Q0 apple_module/D1/SLICE_65 (from circuit_clk)
|
|
ROUTE 1 0.133 R19C31D.Q0 to R19C31B.D0 apple_module/D1/Qe
|
|
CTOF_DEL --- 0.101 R19C31B.D0 to R19C31B.F0 apple_module/D1/SLICE_66
|
|
ROUTE 1 0.000 R19C31B.F0 to R19C31B.DI0 apple_module/D1/Qf_3 (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D1/SLICE_65:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R19C31D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D1/SLICE_66:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R19C31B.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D8/count[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D8/count[3] (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D8/SLICE_79 to apple_module/D8/SLICE_79 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D8/SLICE_79 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R19C33D.CLK to R19C33D.Q1 apple_module/D8/SLICE_79 (from circuit_clk)
|
|
ROUTE 4 0.133 R19C33D.Q1 to R19C33D.A1 apple_module/count[3]
|
|
CTOF_DEL --- 0.101 R19C33D.A1 to R19C33D.F1 apple_module/D8/SLICE_79
|
|
ROUTE 1 0.000 R19C33D.F1 to R19C33D.DI1 apple_module/D8/count_n3 (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D7/count[0] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D7/count[0] (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D7/SLICE_85 to apple_module/D7/SLICE_85 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D7/SLICE_85 to apple_module/D7/SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R17C33C.CLK to R17C33C.Q0 apple_module/D7/SLICE_85 (from circuit_clk)
|
|
ROUTE 6 0.133 R17C33C.Q0 to R17C33C.A0 apple_module/horz_count_upper[0]
|
|
CTOF_DEL --- 0.101 R17C33C.A0 to R17C33C.F0 apple_module/D7/SLICE_85
|
|
ROUTE 1 0.000 R17C33C.F0 to R17C33C.DI0 apple_module/D7/N_12_i (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D7/SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33C.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D7/SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33C.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D15/count[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D15/count[3] (to circuit_clk +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D15/SLICE_92 to apple_module/D15/SLICE_92 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D15/SLICE_92 to apple_module/D15/SLICE_92:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R17C32D.CLK to R17C32D.Q1 apple_module/D15/SLICE_92 (from circuit_clk)
|
|
ROUTE 4 0.133 R17C32D.Q1 to R17C32D.A1 apple_module/sync_count[3]
|
|
CTOF_DEL --- 0.101 R17C32D.A1 to R17C32D.F1 apple_module/D15/SLICE_92
|
|
ROUTE 1 0.000 R17C32D.F1 to R17C32D.DI1 apple_module/D15/N_41_i (to circuit_clk)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D15/SLICE_92:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C32D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D15/SLICE_92:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C32D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.381ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D8/count[2] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/D8/count[2] (to circuit_clk +)
|
|
|
|
Delay: 0.368ns (63.6% logic, 36.4% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.368ns physical path delay apple_module/D8/SLICE_79 to apple_module/D8/SLICE_79 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.381ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D8/SLICE_79 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R19C33D.CLK to R19C33D.Q0 apple_module/D8/SLICE_79 (from circuit_clk)
|
|
ROUTE 6 0.134 R19C33D.Q0 to R19C33D.A0 apple_module/count[2]
|
|
CTOF_DEL --- 0.101 R19C33D.A0 to R19C33D.F0 apple_module/D8/SLICE_79
|
|
ROUTE 1 0.000 R19C33D.F0 to R19C33D.DI0 apple_module/D8/count_n2 (to circuit_clk)
|
|
--------
|
|
0.368 (63.6% logic, 36.4% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path clock_module/PLLInst_0 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path clock_module/PLLInst_0 to apple_module/D8/SLICE_79:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 24 0.707 RPLL.CLKOS to R19C33D.CLK circuit_clk
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
================================================================================
|
|
Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
|
1120 items scored, 37 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Error: The following path exceeds requirements by 3.228ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C13/states[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[2] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.377ns (62.1% logic, 37.9% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.377ns physical path delay apple_module/SLICE_90 to apple_module/SLICE_100 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.618ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.605ns) by 3.228ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_90 to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C31A.CLK to R21C31A.Q1 apple_module/SLICE_90 (from circuit_clk)
|
|
ROUTE 5 0.143 R21C31A.Q1 to R21C30C.C0 apple_module/states[3]
|
|
CTOF_DEL --- 0.101 R21C30C.C0 to R21C30C.F0 apple_module/SLICE_100
|
|
ROUTE 1 0.000 R21C30C.F0 to R21C30C.DI0 apple_module/y2_i (to apple_module/C5/y1)
|
|
--------
|
|
0.377 (62.1% logic, 37.9% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C31A.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_100:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C30C.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 3.156ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D9/count[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[0] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.449ns (52.1% logic, 47.9% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.449ns physical path delay apple_module/D9/SLICE_81 to apple_module/SLICE_89 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.618ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.605ns) by 3.156ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D9/SLICE_81 to apple_module/SLICE_89:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C32C.CLK to R21C32C.Q1 apple_module/D9/SLICE_81 (from circuit_clk)
|
|
ROUTE 6 0.215 R21C32C.Q1 to R21C33B.A0 apple_module/count_0[3]
|
|
CTOF_DEL --- 0.101 R21C33B.A0 to R21C33B.F0 apple_module/SLICE_89
|
|
ROUTE 1 0.000 R21C33B.F0 to R21C33B.DI0 apple_module/last (to apple_module/C5/y1)
|
|
--------
|
|
0.449 (52.1% logic, 47.9% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32C.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_89:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C33B.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.994ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D9/count[2] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[0] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.611ns (54.8% logic, 45.2% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.611ns physical path delay apple_module/D9/SLICE_81 to apple_module/SLICE_89 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.618ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.605ns) by 2.994ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D9/SLICE_81 to apple_module/SLICE_89:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C32C.CLK to R21C32C.Q0 apple_module/D9/SLICE_81 (from circuit_clk)
|
|
ROUTE 5 0.218 R21C32C.Q0 to R21C33B.A1 apple_module/count_0[2]
|
|
CTOF_DEL --- 0.101 R21C33B.A1 to R21C33B.F1 apple_module/SLICE_89
|
|
ROUTE 3 0.058 R21C33B.F1 to R21C33B.C0 apple_module/D9/N_65
|
|
CTOF_DEL --- 0.101 R21C33B.C0 to R21C33B.F0 apple_module/SLICE_89
|
|
ROUTE 1 0.000 R21C33B.F0 to R21C33B.DI0 apple_module/last (to apple_module/C5/y1)
|
|
--------
|
|
0.611 (54.8% logic, 45.2% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D9/SLICE_81:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32C.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_89:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C33B.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.985ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C13/states[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[3] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.620ns (54.0% logic, 46.0% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.620ns physical path delay apple_module/SLICE_90 to apple_module/SLICE_77 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.618ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.605ns) by 2.985ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_90 to apple_module/SLICE_77:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C31A.CLK to R21C31A.Q1 apple_module/SLICE_90 (from circuit_clk)
|
|
ROUTE 5 0.137 R21C31A.Q1 to R21C31A.D1 apple_module/states[3]
|
|
CTOF_DEL --- 0.101 R21C31A.D1 to R21C31A.F1 apple_module/SLICE_90
|
|
ROUTE 2 0.144 R21C31A.F1 to R21C31C.B0 apple_module/y2_1
|
|
CTOF_DEL --- 0.101 R21C31C.B0 to R21C31C.F0 apple_module/SLICE_77
|
|
ROUTE 4 0.004 R21C31C.F0 to R21C31C.DI0 apple_module/clear_char (to apple_module/C5/y1)
|
|
--------
|
|
0.620 (54.0% logic, 46.0% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C31A.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_77:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C31C.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.940ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C13/states[2] (from circuit_clk +)
|
|
Destination: DP8KC Port apple_module/C11b/sram_1_0_0_0(ASIC) (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.801ns (29.2% logic, 70.8% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.801ns physical path delay apple_module/SLICE_90 to apple_module/C11b/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.690ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.741ns) by 2.940ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_90 to apple_module/C11b/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C31A.CLK to R21C31A.Q0 apple_module/SLICE_90 (from circuit_clk)
|
|
ROUTE 1 0.136 R21C31A.Q0 to R21C31D.C0 apple_module/states[2]
|
|
CTOF_DEL --- 0.101 R21C31D.C0 to R21C31D.F0 SLICE_113
|
|
ROUTE 1 0.431 R21C31D.F0 to *R_R20C24.DIA1 apple_module/mem_curs_in[0] (to apple_module/C5/y1)
|
|
--------
|
|
0.801 (29.2% logic, 70.8% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C31A.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/C11b/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.402 R2C19D.F0 to *R_R20C24.CLKA apple_module/C5/y1
|
|
--------
|
|
5.092 (18.8% logic, 81.2% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.899ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/C13/states[3] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[5] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.706ns (47.5% logic, 52.5% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.706ns physical path delay apple_module/SLICE_90 to apple_module/SLICE_93 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.618ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.605ns) by 2.899ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/SLICE_90 to apple_module/SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C31A.CLK to R21C31A.Q1 apple_module/SLICE_90 (from circuit_clk)
|
|
ROUTE 5 0.142 R21C31A.Q1 to R21C30D.C0 apple_module/states[3]
|
|
CTOF_DEL --- 0.101 R21C30D.C0 to R21C30D.F0 apple_module/SLICE_117
|
|
ROUTE 8 0.224 R21C30D.F0 to R21C33D.D0 apple_module/write_i
|
|
CTOF_DEL --- 0.101 R21C33D.D0 to R21C33D.F0 apple_module/SLICE_93
|
|
ROUTE 5 0.005 R21C33D.F0 to R21C33D.DI0 apple_module/wc1_i (to apple_module/C5/y1)
|
|
--------
|
|
0.706 (47.5% logic, 52.5% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C31A.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C33D.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.891ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D6/count[0] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[4] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.696ns (33.6% logic, 66.4% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.696ns physical path delay apple_module/D6/SLICE_84 to apple_module/SLICE_87 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.600ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.587ns) by 2.891ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D6/SLICE_84 to apple_module/SLICE_87:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C33B.CLK to R18C33B.Q0 apple_module/D6/SLICE_84 (from circuit_clk)
|
|
ROUTE 8 0.459 R18C33B.Q0 to R21C32A.B0 apple_module/horz_count_lower[0]
|
|
CTOF_DEL --- 0.101 R21C32A.B0 to R21C32A.F0 apple_module/SLICE_87
|
|
ROUTE 5 0.003 R21C32A.F0 to R21C32A.DI0 apple_module/last_h (to apple_module/C5/y1)
|
|
--------
|
|
0.696 (33.6% logic, 66.4% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D6/SLICE_84:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C33B.CLK circuit_clk
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_87:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C32A.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.838ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D9/count[0] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[0] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.767ns (43.7% logic, 56.3% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.767ns physical path delay apple_module/D9/SLICE_80 to apple_module/SLICE_89 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.618ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.605ns) by 2.838ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D9/SLICE_80 to apple_module/SLICE_89:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R21C32D.CLK to R21C32D.Q0 apple_module/D9/SLICE_80 (from circuit_clk)
|
|
ROUTE 5 0.374 R21C32D.Q0 to R21C33B.C1 apple_module/count_0[0]
|
|
CTOF_DEL --- 0.101 R21C33B.C1 to R21C33B.F1 apple_module/SLICE_89
|
|
ROUTE 3 0.058 R21C33B.F1 to R21C33B.C0 apple_module/D9/N_65
|
|
CTOF_DEL --- 0.101 R21C33B.C0 to R21C33B.F0 apple_module/SLICE_89
|
|
ROUTE 1 0.000 R21C33B.F0 to R21C33B.DI0 apple_module/last (to apple_module/C5/y1)
|
|
--------
|
|
0.767 (43.7% logic, 56.3% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D9/SLICE_80:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.689 RPLL.CLKOS to R21C32D.CLK circuit_clk
|
|
--------
|
|
1.402 (32.0% logic, 68.0% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_89:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C33B.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.827ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D6/count[2] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[4] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.760ns (44.1% logic, 55.9% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.760ns physical path delay apple_module/D6/SLICE_72 to apple_module/SLICE_87 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.600ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.587ns) by 2.827ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D6/SLICE_72 to apple_module/SLICE_87:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C33C.CLK to R18C33C.Q1 apple_module/D6/SLICE_72 (from circuit_clk)
|
|
ROUTE 4 0.140 R18C33C.Q1 to R18C33A.D1 apple_module/D6/count[2]
|
|
CTOF_DEL --- 0.101 R18C33A.D1 to R18C33A.F1 apple_module/D6/SLICE_119
|
|
ROUTE 4 0.282 R18C33A.F1 to R21C32A.C0 apple_module/N_66
|
|
CTOF_DEL --- 0.101 R21C32A.C0 to R21C32A.F0 apple_module/SLICE_87
|
|
ROUTE 5 0.003 R21C32A.F0 to R21C32A.DI0 apple_module/last_h (to apple_module/C5/y1)
|
|
--------
|
|
0.760 (44.1% logic, 55.9% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D6/SLICE_72:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C33C.CLK circuit_clk
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_87:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C32A.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.746ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q apple_module/D6/count[1] (from circuit_clk +)
|
|
Destination: FF Data in apple_module/C7/states[4] (to apple_module/C5/y1 -)
|
|
|
|
Delay: 0.841ns (39.8% logic, 60.2% route), 3 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.841ns physical path delay apple_module/D6/SLICE_72 to apple_module/SLICE_87 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.600ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.587ns) by 2.746ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path apple_module/D6/SLICE_72 to apple_module/SLICE_87:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R18C33C.CLK to R18C33C.Q0 apple_module/D6/SLICE_72 (from circuit_clk)
|
|
ROUTE 4 0.221 R18C33C.Q0 to R18C33A.A1 apple_module/D6/count[1]
|
|
CTOF_DEL --- 0.101 R18C33A.A1 to R18C33A.F1 apple_module/D6/SLICE_119
|
|
ROUTE 4 0.282 R18C33A.F1 to R21C32A.C0 apple_module/N_66
|
|
CTOF_DEL --- 0.101 R21C32A.C0 to R21C32A.F0 apple_module/SLICE_87
|
|
ROUTE 5 0.003 R21C32A.F0 to R21C32A.DI0 apple_module/last_h (to apple_module/C5/y1)
|
|
--------
|
|
0.841 (39.8% logic, 60.2% route), 3 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path sys_clock to apple_module/D6/SLICE_72:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R18C33C.CLK circuit_clk
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Destination Clock Path sys_clock to apple_module/SLICE_87:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI sys_clock
|
|
ROUTE 38 0.264 126.PADDI to RPLL.CLKI sys_clock_c
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS clock_module/PLLInst_0
|
|
ROUTE 24 0.707 RPLL.CLKOS to R17C33B.CLK circuit_clk
|
|
REG_DEL --- 0.154 R17C33B.CLK to R17C33B.Q0 apple_module/D7/SLICE_86
|
|
ROUTE 12 0.498 R17C33B.Q0 to R21C32B.D1 apple_module/horz_count_upper[3]
|
|
CTOF_DEL --- 0.177 R21C32B.D1 to R21C32B.F1 apple_module/SLICE_118
|
|
ROUTE 7 1.264 R21C32B.F1 to R2C19D.B0 apple_module/vbl_i
|
|
CTOF_DEL --- 0.177 R2C19D.B0 to R2C19D.F0 apple_module/SLICE_127
|
|
ROUTE 47 1.330 R2C19D.F0 to R21C32A.CLK apple_module/C5/y1
|
|
--------
|
|
5.020 (19.1% logic, 80.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB clock_module/PLLInst_0
|
|
ROUTE 1 0.000 RPLL.CLKINTFB to RPLL.CLKFB clock_module/CLKFB_t
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
Report Summary
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY NET "sys_clock_c" 25.000000 | | |
|
|
MHz ; | 0.000 ns| 0.379 ns| 2
|
|
| | |
|
|
FREQUENCY NET "circuit_clk" 14.285714 | | |
|
|
MHz ; | 0.000 ns| 0.379 ns| 2
|
|
| | |
|
|
FREQUENCY PORT "sys_clock" 25.000000 | | |
|
|
MHz ; | -| -| 2 *
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
1 preference(marked by "*" above) not met.
|
|
|
|
----------------------------------------------------------------------------
|
|
Critical Nets | Loads| Errors| % of total
|
|
----------------------------------------------------------------------------
|
|
apple_module/last_h | 5| 16| 43.24%
|
|
| | |
|
|
apple_module/last | 1| 16| 43.24%
|
|
| | |
|
|
apple_module/states[3] | 5| 12| 32.43%
|
|
| | |
|
|
apple_module/N_8 | 3| 8| 21.62%
|
|
| | |
|
|
apple_module/write_i | 8| 7| 18.92%
|
|
| | |
|
|
apple_module/N_66 | 4| 6| 16.22%
|
|
| | |
|
|
apple_module/N_27 | 2| 4| 10.81%
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
Clock Domains Analysis
|
|
------------------------
|
|
|
|
Found 9 clocks:
|
|
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 18
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
|
|
|
|
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: clock_module/CLKFB_t Source: clock_module/PLLInst_0.CLKINTFB Loads: 1
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 6
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
|
|
|
|
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
|
|
|
|
Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 24
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 6
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 4
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 7
|
|
|
|
Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 38
|
|
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
|
Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ; Transfers: 1
|
|
|
|
|
|
Timing summary (Hold):
|
|
---------------
|
|
|
|
Timing errors: 37 Score: 79282
|
|
Cumulative negative slack: 79282
|
|
|
|
Constraints cover 3276 paths, 9 nets, and 1223 connections (98.47% coverage)
|
|
|
|
|
|
|
|
Timing summary (Setup and Hold):
|
|
---------------
|
|
|
|
Timing errors: 175 (setup), 37 (hold)
|
|
Score: 8347444 (setup), 79282 (hold)
|
|
Cumulative negative slack: 8426726 (8347444+79282)
|
|
--------------------------------------------------------------------------------
|
|
|
|
--------------------------------------------------------------------------------
|
|
|