97 lines
3.6 KiB
Tcl
97 lines
3.6 KiB
Tcl
#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file
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#device options
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set_option -technology MACHXO2
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set_option -part LCMXO2_7000HC
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set_option -package TG144C
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set_option -speed_grade -4
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#compilation/mapping options
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set_option -symbolic_fsm_compiler true
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set_option -resource_sharing true
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#use verilog 2001 standard option
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set_option -vlog_std v2001
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#map options
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set_option -frequency auto
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set_option -maxfan 1000
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set_option -auto_constrain_io 0
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set_option -disable_io_insertion false
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set_option -retiming false; set_option -pipe true
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set_option -force_gsr false
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set_option -compiler_compatible 0
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set_option -dup false
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set_option -frequency 1
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set_option -default_enum_encoding default
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#simulation options
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#timing analysis options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#synplifyPro options
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set_option -fix_gated_and_generated_clocks 1
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set_option -update_models_cp 0
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set_option -resolve_multiple_driver 0
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#-- add_file options
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add_file -vhdl {C:/lscc/diamond/3.10_x64/cae_library/synthesis/vhdl/machxo2.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/impl1/source/FleaFPGA_Uno_Top.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/impl1/Apple1Display.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/impl1/source/ntsc.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/impl1/divider.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/impl1/master_clk.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7400.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7402.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7404.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7408.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7410.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7427.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7432.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm7450.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm74157.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm74160.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm74161.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm74166.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm74174.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm74175.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/2504.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/2519.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/dm2513.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/CharacterRom.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ScreenRom.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ShiftReg40.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/test_entity.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ShiftReg1024.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ScreenRom2.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ScreenRam.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/CursorRam.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/UART_RX.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/ttl/ne555.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/sig2504.vhd}
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add_file -vhdl -lib "work" {C:/Dev/Apple1Display/sig2513.vhd}
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#-- top module name
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set_option -top_module FleaFPGA_Uno_E1
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#-- set result format/file last
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project -result_file {C:/Dev/Apple1Display/impl1/Apple1Display_impl1.edi}
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#-- error message log file
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project -log_file {Apple1Display_impl1.srf}
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#-- set any command lines input by customer
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#-- run Synplify with 'arrange HDL file'
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project -run hdl_info_gen -fileorder
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project -run
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