1385 lines
109 KiB
HTML
1385 lines
109 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<HTML><HEAD>
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<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
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<STYLE type=text/css>
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.msb {font-size: 9pt; font-family: monospace; font-weight: bold }
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<META content="MSHTML 6.00.2900.2180" name=GENERATOR></HEAD>
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<BODY><B>
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</B>
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<BR><PRE><A name="Report Header"></A>
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.2.115
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Mon Aug 05 08:38:33 2019
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Design file: FleaFPGA_Uno_E1
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Device,speed: LCMXO2-7000HC,M
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Report level: verbose report, limited to 10 items per preference
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--------------------------------------------------------------------------------
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</A><A name="FREQUENCY NET 'sys_clock_c' 25.000000 MH"></A>================================================================================
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Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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</A><A name="FREQUENCY NET 'circuit_clk' 14.285714 MH"></A>================================================================================
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Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
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10 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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<font color=#000000>
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Passed: The following path meets requirements by 0.379ns
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/count[1]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
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Destination: FF Data in <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/count[1]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
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Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
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Constraint Details:
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0.366ns physical path delay apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.379ns
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Physical Path Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R16C17D.CLK,R16C17D.Q1,apple_module/D6/SLICE_23:ROUTE, 0.132,R16C17D.Q1,R16C17D.A1,apple_module/D6/count[1]:CTOF_DEL, 0.101,R16C17D.A1,R16C17D.F1,apple_module/D6/SLICE_23:ROUTE, 0.000,R16C17D.F1,R16C17D.DI1,apple_module/D6/count_n1">Data path</A> apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 R16C17D.CLK to R16C17D.Q1 <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/SLICE_23</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
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ROUTE 4 0.132<A href="#@net:apple_module/D6/count[1]:R16C17D.Q1:R16C17D.A1:0.132"> R16C17D.Q1 to R16C17D.A1 </A> <A href="#@net:apple_module/D6/count[1]">apple_module/D6/count[1]</A>
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CTOF_DEL --- 0.101 R16C17D.A1 to R16C17D.F1 <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/SLICE_23</A>
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ROUTE 1 0.000<A href="#@net:apple_module/D6/count_n1:R16C17D.F1:R16C17D.DI1:0.000"> R16C17D.F1 to R16C17D.DI1 </A> <A href="#@net:apple_module/D6/count_n1">apple_module/D6/count_n1</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
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--------
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0.366 (63.9% logic, 36.1% route), 2 logic levels.
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Clock Skew Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R16C17D.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D6/SLICE_23:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R16C17D.CLK:0.707"> RPLL.CLKOS to R16C17D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R16C17D.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D6/SLICE_23:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R16C17D.CLK:0.707"> RPLL.CLKOS to R16C17D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 0.379ns
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:apple_module/D15/SLICE_22">apple_module/D15/count[2]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
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Destination: FF Data in <A href="#@comp:apple_module/D15/SLICE_22">apple_module/D15/count[2]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
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Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
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Constraint Details:
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0.366ns physical path delay apple_module/D15/SLICE_22 to apple_module/D15/SLICE_22 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.379ns
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Physical Path Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R15C17A.CLK,R15C17A.Q1,apple_module/D15/SLICE_22:ROUTE, 0.132,R15C17A.Q1,R15C17A.A1,apple_module/D15/count[2]:CTOF_DEL, 0.101,R15C17A.A1,R15C17A.F1,apple_module/D15/SLICE_22:ROUTE, 0.000,R15C17A.F1,R15C17A.DI1,apple_module/D15/count_n2">Data path</A> apple_module/D15/SLICE_22 to apple_module/D15/SLICE_22:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 R15C17A.CLK to R15C17A.Q1 <A href="#@comp:apple_module/D15/SLICE_22">apple_module/D15/SLICE_22</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
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ROUTE 3 0.132<A href="#@net:apple_module/D15/count[2]:R15C17A.Q1:R15C17A.A1:0.132"> R15C17A.Q1 to R15C17A.A1 </A> <A href="#@net:apple_module/D15/count[2]">apple_module/D15/count[2]</A>
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CTOF_DEL --- 0.101 R15C17A.A1 to R15C17A.F1 <A href="#@comp:apple_module/D15/SLICE_22">apple_module/D15/SLICE_22</A>
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ROUTE 1 0.000<A href="#@net:apple_module/D15/count_n2:R15C17A.F1:R15C17A.DI1:0.000"> R15C17A.F1 to R15C17A.DI1 </A> <A href="#@net:apple_module/D15/count_n2">apple_module/D15/count_n2</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
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--------
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0.366 (63.9% logic, 36.1% route), 2 logic levels.
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Clock Skew Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R15C17A.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D15/SLICE_22:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C17A.CLK:0.707"> RPLL.CLKOS to R15C17A.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R15C17A.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D15/SLICE_22:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C17A.CLK:0.707"> RPLL.CLKOS to R15C17A.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 0.379ns
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:apple_module/SLICE_48">apple_module/C13/states_ret</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
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Destination: FF Data in <A href="#@comp:apple_module/SLICE_48">apple_module/C13/states_ret</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
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Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
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Constraint Details:
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0.366ns physical path delay apple_module/SLICE_48 to apple_module/SLICE_48 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.379ns
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Physical Path Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R16C15B.CLK,R16C15B.Q0,apple_module/SLICE_48:ROUTE, 0.132,R16C15B.Q0,R16C15B.A0,apple_module/states_ret_Q:CTOF_DEL, 0.101,R16C15B.A0,R16C15B.F0,apple_module/SLICE_48:ROUTE, 0.000,R16C15B.F0,R16C15B.DI0,apple_module/dot_rate_0_i">Data path</A> apple_module/SLICE_48 to apple_module/SLICE_48:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 R16C15B.CLK to R16C15B.Q0 <A href="#@comp:apple_module/SLICE_48">apple_module/SLICE_48</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
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ROUTE 12 0.132<A href="#@net:apple_module/states_ret_Q:R16C15B.Q0:R16C15B.A0:0.132"> R16C15B.Q0 to R16C15B.A0 </A> <A href="#@net:apple_module/states_ret_Q">apple_module/states_ret_Q</A>
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CTOF_DEL --- 0.101 R16C15B.A0 to R16C15B.F0 <A href="#@comp:apple_module/SLICE_48">apple_module/SLICE_48</A>
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ROUTE 1 0.000<A href="#@net:apple_module/dot_rate_0_i:R16C15B.F0:R16C15B.DI0:0.000"> R16C15B.F0 to R16C15B.DI0 </A> <A href="#@net:apple_module/dot_rate_0_i">apple_module/dot_rate_0_i</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
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--------
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0.366 (63.9% logic, 36.1% route), 2 logic levels.
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Clock Skew Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R16C15B.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/SLICE_48:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R16C15B.CLK:0.707"> RPLL.CLKOS to R16C15B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R16C15B.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/SLICE_48:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R16C15B.CLK:0.707"> RPLL.CLKOS to R16C15B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 0.379ns
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:apple_module/D11/SLICE_21">apple_module/D11/count[1]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
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Destination: FF Data in <A href="#@comp:apple_module/D11/SLICE_21">apple_module/D11/count[1]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
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Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
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Constraint Details:
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0.366ns physical path delay apple_module/D11/SLICE_21 to apple_module/D11/SLICE_21 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.379ns
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Physical Path Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R14C19A.CLK,R14C19A.Q1,apple_module/D11/SLICE_21:ROUTE, 0.132,R14C19A.Q1,R14C19A.A1,apple_module/D11/count[1]:CTOF_DEL, 0.101,R14C19A.A1,R14C19A.F1,apple_module/D11/SLICE_21:ROUTE, 0.000,R14C19A.F1,R14C19A.DI1,apple_module/D11/count_5[1]">Data path</A> apple_module/D11/SLICE_21 to apple_module/D11/SLICE_21:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 R14C19A.CLK to R14C19A.Q1 <A href="#@comp:apple_module/D11/SLICE_21">apple_module/D11/SLICE_21</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
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ROUTE 4 0.132<A href="#@net:apple_module/D11/count[1]:R14C19A.Q1:R14C19A.A1:0.132"> R14C19A.Q1 to R14C19A.A1 </A> <A href="#@net:apple_module/D11/count[1]">apple_module/D11/count[1]</A>
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CTOF_DEL --- 0.101 R14C19A.A1 to R14C19A.F1 <A href="#@comp:apple_module/D11/SLICE_21">apple_module/D11/SLICE_21</A>
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ROUTE 1 0.000<A href="#@net:apple_module/D11/count_5[1]:R14C19A.F1:R14C19A.DI1:0.000"> R14C19A.F1 to R14C19A.DI1 </A> <A href="#@net:apple_module/D11/count_5[1]">apple_module/D11/count_5[1]</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
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--------
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0.366 (63.9% logic, 36.1% route), 2 logic levels.
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Clock Skew Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C19A.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D11/SLICE_21:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C19A.CLK:0.707"> RPLL.CLKOS to R14C19A.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C19A.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D11/SLICE_21:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C19A.CLK:0.707"> RPLL.CLKOS to R14C19A.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
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--------
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0.707 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 0.379ns
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/count[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
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Destination: FF Data in <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/count[3]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
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Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
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Constraint Details:
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0.366ns physical path delay apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.379ns
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Physical Path Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.132,R14C18D.Q1,R14C18D.A1,apple_module/count_0[3]:CTOF_DEL, 0.101,R14C18D.A1,R14C18D.F1,apple_module/D9/SLICE_34:ROUTE, 0.000,R14C18D.F1,R14C18D.DI1,apple_module/D9/N_39_i_i">Data path</A> apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
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ROUTE 3 0.132<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18D.A1:0.132"> R14C18D.Q1 to R14C18D.A1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
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CTOF_DEL --- 0.101 R14C18D.A1 to R14C18D.F1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
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ROUTE 1 0.000<A href="#@net:apple_module/D9/N_39_i_i:R14C18D.F1:R14C18D.DI1:0.000"> R14C18D.F1 to R14C18D.DI1 </A> <A href="#@net:apple_module/D9/N_39_i_i">apple_module/D9/N_39_i_i</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
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--------
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0.366 (63.9% logic, 36.1% route), 2 logic levels.
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Clock Skew Details:
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<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D9/SLICE_34:
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Name Fanout Delay (ns) Site Resource
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ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D9/SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/count[0]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: FF Data in <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/count[0]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R16C17D.CLK,R16C17D.Q0,apple_module/D6/SLICE_23:ROUTE, 0.132,R16C17D.Q0,R16C17D.A0,apple_module/D6/count[0]:CTOF_DEL, 0.101,R16C17D.A0,R16C17D.F0,apple_module/D6/SLICE_23:ROUTE, 0.000,R16C17D.F0,R16C17D.DI0,apple_module/D6/count_n0">Data path</A> apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R16C17D.CLK to R16C17D.Q0 <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/SLICE_23</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 5 0.132<A href="#@net:apple_module/D6/count[0]:R16C17D.Q0:R16C17D.A0:0.132"> R16C17D.Q0 to R16C17D.A0 </A> <A href="#@net:apple_module/D6/count[0]">apple_module/D6/count[0]</A>
|
|
CTOF_DEL --- 0.101 R16C17D.A0 to R16C17D.F0 <A href="#@comp:apple_module/D6/SLICE_23">apple_module/D6/SLICE_23</A>
|
|
ROUTE 1 0.000<A href="#@net:apple_module/D6/count_n0:R16C17D.F0:R16C17D.DI0:0.000"> R16C17D.F0 to R16C17D.DI0 </A> <A href="#@net:apple_module/D6/count_n0">apple_module/D6/count_n0</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R16C17D.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D6/SLICE_23:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R16C17D.CLK:0.707"> RPLL.CLKOS to R16C17D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R16C17D.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D6/SLICE_23:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R16C17D.CLK:0.707"> RPLL.CLKOS to R16C17D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/D7/SLICE_42">apple_module/D7/count[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: FF Data in <A href="#@comp:apple_module/D7/SLICE_42">apple_module/D7/count[3]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D7/SLICE_42 to apple_module/D7/SLICE_42 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R15C18B.CLK,R15C18B.Q0,apple_module/D7/SLICE_42:ROUTE, 0.133,R15C18B.Q0,R15C18B.A0,apple_module/horz_count_upper[3]:CTOF_DEL, 0.101,R15C18B.A0,R15C18B.F0,apple_module/D7/SLICE_42:ROUTE, 0.000,R15C18B.F0,R15C18B.DI0,apple_module/D7/count_n3">Data path</A> apple_module/D7/SLICE_42 to apple_module/D7/SLICE_42:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R15C18B.CLK to R15C18B.Q0 <A href="#@comp:apple_module/D7/SLICE_42">apple_module/D7/SLICE_42</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 11 0.133<A href="#@net:apple_module/horz_count_upper[3]:R15C18B.Q0:R15C18B.A0:0.133"> R15C18B.Q0 to R15C18B.A0 </A> <A href="#@net:apple_module/horz_count_upper[3]">apple_module/horz_count_upper[3]</A>
|
|
CTOF_DEL --- 0.101 R15C18B.A0 to R15C18B.F0 <A href="#@comp:apple_module/D7/SLICE_42">apple_module/D7/SLICE_42</A>
|
|
ROUTE 1 0.000<A href="#@net:apple_module/D7/count_n3:R15C18B.F0:R15C18B.DI0:0.000"> R15C18B.F0 to R15C18B.DI0 </A> <A href="#@net:apple_module/D7/count_n3">apple_module/D7/count_n3</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R15C18B.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D7/SLICE_42:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18B.CLK:0.707"> RPLL.CLKOS to R15C18B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R15C18B.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D7/SLICE_42:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18B.CLK:0.707"> RPLL.CLKOS to R15C18B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/count[2]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: FF Data in <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/count[2]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R14C18D.CLK,R14C18D.Q0,apple_module/D9/SLICE_34:ROUTE, 0.133,R14C18D.Q0,R14C18D.A0,apple_module/count_0[2]:CTOF_DEL, 0.101,R14C18D.A0,R14C18D.F0,apple_module/D9/SLICE_34:ROUTE, 0.000,R14C18D.F0,R14C18D.DI0,apple_module/D9/N_44_i_i">Data path</A> apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C18D.CLK to R14C18D.Q0 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 4 0.133<A href="#@net:apple_module/count_0[2]:R14C18D.Q0:R14C18D.A0:0.133"> R14C18D.Q0 to R14C18D.A0 </A> <A href="#@net:apple_module/count_0[2]">apple_module/count_0[2]</A>
|
|
CTOF_DEL --- 0.101 R14C18D.A0 to R14C18D.F0 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
|
|
ROUTE 1 0.000<A href="#@net:apple_module/D9/N_44_i_i:R14C18D.F0:R14C18D.DI0:0.000"> R14C18D.F0 to R14C18D.DI0 </A> <A href="#@net:apple_module/D9/N_44_i_i">apple_module/D9/N_44_i_i</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D9/SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D9/SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/count[0]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: FF Data in <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/count[0]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D7/SLICE_41 to apple_module/D7/SLICE_41 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R15C18D.CLK,R15C18D.Q0,apple_module/D7/SLICE_41:ROUTE, 0.133,R15C18D.Q0,R15C18D.A0,apple_module/horz_count_upper[0]:CTOF_DEL, 0.101,R15C18D.A0,R15C18D.F0,apple_module/D7/SLICE_41:ROUTE, 0.000,R15C18D.F0,R15C18D.DI0,apple_module/D7/N_12_i">Data path</A> apple_module/D7/SLICE_41 to apple_module/D7/SLICE_41:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R15C18D.CLK to R15C18D.Q0 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 6 0.133<A href="#@net:apple_module/horz_count_upper[0]:R15C18D.Q0:R15C18D.A0:0.133"> R15C18D.Q0 to R15C18D.A0 </A> <A href="#@net:apple_module/horz_count_upper[0]">apple_module/horz_count_upper[0]</A>
|
|
CTOF_DEL --- 0.101 R15C18D.A0 to R15C18D.F0 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 1 0.000<A href="#@net:apple_module/D7/N_12_i:R15C18D.F0:R15C18D.DI0:0.000"> R15C18D.F0 to R15C18D.DI0 </A> <A href="#@net:apple_module/D7/N_12_i">apple_module/D7/N_12_i</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D7/SLICE_41:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D7/SLICE_41:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/D11/SLICE_35">apple_module/D11/count_0[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: FF Data in <A href="#@comp:apple_module/D11/SLICE_35">apple_module/D11/count_0[3]</A> (to <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay apple_module/D11/SLICE_35 to apple_module/D11/SLICE_35 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:REG_DEL, 0.133,R14C19D.CLK,R14C19D.Q0,apple_module/D11/SLICE_35:ROUTE, 0.133,R14C19D.Q0,R14C19D.A0,apple_module/count_i[3]:CTOF_DEL, 0.101,R14C19D.A0,R14C19D.F0,apple_module/D11/SLICE_35:ROUTE, 0.000,R14C19D.F0,R14C19D.DI0,apple_module/D11/count_5_0_0[3]">Data path</A> apple_module/D11/SLICE_35 to apple_module/D11/SLICE_35:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C19D.CLK to R14C19D.Q0 <A href="#@comp:apple_module/D11/SLICE_35">apple_module/D11/SLICE_35</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 8 0.133<A href="#@net:apple_module/count_i[3]:R14C19D.Q0:R14C19D.A0:0.133"> R14C19D.Q0 to R14C19D.A0 </A> <A href="#@net:apple_module/count_i[3]">apple_module/count_i[3]</A>
|
|
CTOF_DEL --- 0.101 R14C19D.A0 to R14C19D.F0 <A href="#@comp:apple_module/D11/SLICE_35">apple_module/D11/SLICE_35</A>
|
|
ROUTE 1 0.000<A href="#@net:apple_module/D11/count_5_0_0[3]:R14C19D.F0:R14C19D.DI0:0.000"> R14C19D.F0 to R14C19D.DI0 </A> <A href="#@net:apple_module/D11/count_5_0_0[3]">apple_module/D11/count_5_0_0[3]</A> (to <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C19D.CLK,circuit_clk">Source Clock Path</A> clock_module/PLLInst_0 to apple_module/D11/SLICE_35:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C19D.CLK:0.707"> RPLL.CLKOS to R14C19D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY NET 'circuit_clk' 14.285714 MHz ;:ROUTE, 0.707,RPLL.CLKOS,R14C19D.CLK,circuit_clk">Destination Clock Path</A> clock_module/PLLInst_0 to apple_module/D11/SLICE_35:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C19D.CLK:0.707"> RPLL.CLKOS to R14C19D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
0.707 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
</A><A name="FREQUENCY PORT 'sys_clock' 25.000000 MH"></A>================================================================================
|
|
Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
|
10 items scored, 10 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.665ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: FF Data in <A href="#@comp:apple_module/SLICE_46">apple_module/C7/states[2]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.375ns (62.4% logic, 37.6% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.375ns physical path delay apple_module/SLICE_47 to apple_module/SLICE_46 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
-3.053ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.040ns) by 2.665ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.141,R14C14B.Q1,R14C14C.D0,apple_module/states[3]:CTOF_DEL, 0.101,R14C14C.D0,R14C14C.F0,apple_module/SLICE_46:ROUTE, 0.000,R14C14C.F0,R14C14C.DI0,apple_module/C7/accept_char_i">Data path</A> apple_module/SLICE_47 to apple_module/SLICE_46:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.141<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C14C.D0:0.141"> R14C14B.Q1 to R14C14C.D0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C14C.D0 to R14C14C.F0 <A href="#@comp:apple_module/SLICE_46">apple_module/SLICE_46</A>
|
|
ROUTE 1 0.000<A href="#@net:apple_module/C7/accept_char_i:R14C14C.F0:R14C14C.DI0:0.000"> R14C14C.F0 to R14C14C.DI0 </A> <A href="#@net:apple_module/C7/accept_char_i">apple_module/C7/accept_char_i</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.375 (62.4% logic, 37.6% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.348,R2C19C.F0,R14C14C.CLK,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/SLICE_46:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.348<A href="#@net:apple_module/mem0:R2C19C.F0:R14C14C.CLK:1.348"> R2C19C.F0 to R14C14C.CLK </A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.473 (21.4% logic, 78.6% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.460ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.698ns (33.5% logic, 66.5% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.698ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.460ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.144,R14C14B.Q1,R14C14D.C0,apple_module/states[3]:CTOF_DEL, 0.101,R14C14D.C0,R14C14D.F0,apple_module/SLICE_53:ROUTE, 0.320,R14C14D.F0,EBR_R13C10.DIA5,apple_module/un1_a_1[0]">Data path</A> apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.144<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C14D.C0:0.144"> R14C14B.Q1 to R14C14D.C0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C14D.C0 to R14C14D.F0 <A href="#@comp:apple_module/SLICE_53">apple_module/SLICE_53</A>
|
|
ROUTE 2 0.320<A href="#@net:apple_module/un1_a_1[0]:R14C14D.F0:EBR_R13C10.DIA5:0.320"> R14C14D.F0 to EBR_R13C10.DIA5</A> <A href="#@net:apple_module/un1_a_1[0]">apple_module/un1_a_1[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.698 (33.5% logic, 66.5% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.305ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.853ns (27.4% logic, 72.6% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.853ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.305ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.266,R14C14B.Q1,R14C15D.D0,apple_module/states[3]:CTOF_DEL, 0.101,R14C15D.D0,R14C15D.F0,apple_module/SLICE_55:ROUTE, 0.353,R14C15D.F0,EBR_R13C10.DIA3,apple_module/buffer_char_in[3]">Data path</A> apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.266<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C15D.D0:0.266"> R14C14B.Q1 to R14C15D.D0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C15D.D0 to R14C15D.F0 <A href="#@comp:apple_module/SLICE_55">apple_module/SLICE_55</A>
|
|
ROUTE 2 0.353<A href="#@net:apple_module/buffer_char_in[3]:R14C15D.F0:EBR_R13C10.DIA3:0.353"> R14C15D.F0 to EBR_R13C10.DIA3</A> <A href="#@net:apple_module/buffer_char_in[3]">apple_module/buffer_char_in[3]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.853 (27.4% logic, 72.6% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.257ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.901ns (26.0% logic, 74.0% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.901ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.257ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.234,R14C14B.Q1,R14C15A.B0,apple_module/states[3]:CTOF_DEL, 0.101,R14C15A.B0,R14C15A.F0,apple_module/SLICE_54:ROUTE, 0.433,R14C15A.F0,EBR_R13C10.DIA4,apple_module/un1_a_3[0]">Data path</A> apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.234<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C15A.B0:0.234"> R14C14B.Q1 to R14C15A.B0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C15A.B0 to R14C15A.F0 <A href="#@comp:apple_module/SLICE_54">apple_module/SLICE_54</A>
|
|
ROUTE 2 0.433<A href="#@net:apple_module/un1_a_3[0]:R14C15A.F0:EBR_R13C10.DIA4:0.433"> R14C15A.F0 to EBR_R13C10.DIA4</A> <A href="#@net:apple_module/un1_a_3[0]">apple_module/un1_a_3[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.901 (26.0% logic, 74.0% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.225ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.933ns (25.1% logic, 74.9% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.933ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.225ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.266,R14C14B.Q1,R14C15C.D0,apple_module/states[3]:CTOF_DEL, 0.101,R14C15C.D0,R14C15C.F0,apple_module/SLICE_58:ROUTE, 0.433,R14C15C.F0,EBR_R13C10.DIA0,apple_module/buffer_char_in[0]">Data path</A> apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.266<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C15C.D0:0.266"> R14C14B.Q1 to R14C15C.D0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C15C.D0 to R14C15C.F0 <A href="#@comp:apple_module/SLICE_58">apple_module/SLICE_58</A>
|
|
ROUTE 2 0.433<A href="#@net:apple_module/buffer_char_in[0]:R14C15C.F0:EBR_R13C10.DIA0:0.433"> R14C15C.F0 to EBR_R13C10.DIA0</A> <A href="#@net:apple_module/buffer_char_in[0]">apple_module/buffer_char_in[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.933 (25.1% logic, 74.9% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.201ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[2]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/CursorBuffer/sram_1_0_0_0">apple_module/CursorBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.957ns (24.5% logic, 75.5% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.957ns physical path delay apple_module/SLICE_47 to apple_module/CursorBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.201ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q0,apple_module/SLICE_47:ROUTE, 0.222,R14C14B.Q0,R14C14C.B1,apple_module/states[2]:CTOF_DEL, 0.101,R14C14C.B1,R14C14C.F1,apple_module/SLICE_46:ROUTE, 0.501,R14C14C.F1,EBR_R20C10.DIA1,apple_module/mem_curs_in[0]">Data path</A> apple_module/SLICE_47 to apple_module/CursorBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q0 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 1 0.222<A href="#@net:apple_module/states[2]:R14C14B.Q0:R14C14C.B1:0.222"> R14C14B.Q0 to R14C14C.B1 </A> <A href="#@net:apple_module/states[2]">apple_module/states[2]</A>
|
|
CTOF_DEL --- 0.101 R14C14C.B1 to R14C14C.F1 <A href="#@comp:apple_module/SLICE_46">apple_module/SLICE_46</A>
|
|
ROUTE 1 0.501<A href="#@net:apple_module/mem_curs_in[0]:R14C14C.F1:EBR_R20C10.DIA1:0.501"> R14C14C.F1 to EBR_R20C10.DIA1</A> <A href="#@net:apple_module/mem_curs_in[0]">apple_module/mem_curs_in[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.957 (24.5% logic, 75.5% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R20C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/CursorBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R20C10.CLKA:1.402"> R2C19C.F0 to EBR_R20C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.201ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.957ns (24.5% logic, 75.5% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.957ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.201ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.266,R14C14B.Q1,R14C15B.D0,apple_module/states[3]:CTOF_DEL, 0.101,R14C15B.D0,R14C15B.F0,apple_module/SLICE_56:ROUTE, 0.457,R14C15B.F0,EBR_R13C10.DIA2,apple_module/buffer_char_in[2]">Data path</A> apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.266<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C15B.D0:0.266"> R14C14B.Q1 to R14C15B.D0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C15B.D0 to R14C15B.F0 <A href="#@comp:apple_module/SLICE_56">apple_module/SLICE_56</A>
|
|
ROUTE 2 0.457<A href="#@net:apple_module/buffer_char_in[2]:R14C15B.F0:EBR_R13C10.DIA2:0.457"> R14C15B.F0 to EBR_R13C10.DIA2</A> <A href="#@net:apple_module/buffer_char_in[2]">apple_module/buffer_char_in[2]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.957 (24.5% logic, 75.5% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 2.178ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_47">apple_module/C13/states[3]</A> (from <A href="#@net:circuit_clk">circuit_clk</A> +)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.980ns (23.9% logic, 76.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.980ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-3.107ns skew less
|
|
0.000ns feedback compensation requirement (totaling 3.158ns) by 2.178ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C14B.CLK,R14C14B.Q1,apple_module/SLICE_47:ROUTE, 0.393,R14C14B.Q1,R14C14A.D0,apple_module/states[3]:CTOF_DEL, 0.101,R14C14A.D0,R14C14A.F0,apple_module/SLICE_57:ROUTE, 0.353,R14C14A.F0,EBR_R13C10.DIA1,apple_module/buffer_char_in[1]">Data path</A> apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R14C14B.CLK to R14C14B.Q1 <A href="#@comp:apple_module/SLICE_47">apple_module/SLICE_47</A> (from <A href="#@net:circuit_clk">circuit_clk</A>)
|
|
ROUTE 9 0.393<A href="#@net:apple_module/states[3]:R14C14B.Q1:R14C14A.D0:0.393"> R14C14B.Q1 to R14C14A.D0 </A> <A href="#@net:apple_module/states[3]">apple_module/states[3]</A>
|
|
CTOF_DEL --- 0.101 R14C14A.D0 to R14C14A.F0 <A href="#@comp:apple_module/SLICE_57">apple_module/SLICE_57</A>
|
|
ROUTE 2 0.353<A href="#@net:apple_module/buffer_char_in[1]:R14C14A.F0:EBR_R13C10.DIA1:0.353"> R14C14A.F0 to EBR_R13C10.DIA1</A> <A href="#@net:apple_module/buffer_char_in[1]">apple_module/buffer_char_in[1]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.980 (23.9% logic, 76.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C14B.CLK,circuit_clk">Source Clock Path</A> sys_clock to apple_module/SLICE_47:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C14B.CLK:0.707"> RPLL.CLKOS to R14C14B.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
--------
|
|
1.420 (31.6% logic, 68.4% route), 2 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 0.719ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_45">apple_module/rd[7]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.808ns (29.0% logic, 71.0% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.808ns physical path delay apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-1.476ns skew less
|
|
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.719ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15B.CLK,R15C15B.Q1,apple_module/SLICE_45:ROUTE, 0.254,R15C15B.Q1,R14C14D.D0,apple_module/rd[7]:CTOF_DEL, 0.101,R14C14D.D0,R14C14D.F0,apple_module/SLICE_53:ROUTE, 0.320,R14C14D.F0,EBR_R13C10.DIA5,apple_module/un1_a_1[0]">Data path</A> apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R15C15B.CLK to R15C15B.Q1 <A href="#@comp:apple_module/SLICE_45">apple_module/SLICE_45</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
|
|
ROUTE 1 0.254<A href="#@net:apple_module/rd[7]:R15C15B.Q1:R14C14D.D0:0.254"> R15C15B.Q1 to R14C14D.D0 </A> <A href="#@net:apple_module/rd[7]">apple_module/rd[7]</A>
|
|
CTOF_DEL --- 0.101 R14C14D.D0 to R14C14D.F0 <A href="#@comp:apple_module/SLICE_53">apple_module/SLICE_53</A>
|
|
ROUTE 2 0.320<A href="#@net:apple_module/un1_a_1[0]:R14C14D.F0:EBR_R13C10.DIA5:0.320"> R14C14D.F0 to EBR_R13C10.DIA5</A> <A href="#@net:apple_module/un1_a_1[0]">apple_module/un1_a_1[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.808 (29.0% logic, 71.0% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15B.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_45:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
|
|
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
|
|
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
|
|
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15B.CLK:1.031"> R14C18C.F1 to R15C15B.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
|
|
--------
|
|
3.051 (25.6% logic, 74.4% route), 4 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
<font color=#FF0000>
|
|
|
|
Error: The following path exceeds requirements by 0.689ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:apple_module/SLICE_45">apple_module/rd[5]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
|
|
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
|
|
|
|
Delay: 0.838ns (27.9% logic, 72.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.838ns physical path delay apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
|
|
0.051ns DATA_HLD and
|
|
0.000ns delay constraint less
|
|
-1.476ns skew less
|
|
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.689ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15B.CLK,R15C15B.Q0,apple_module/SLICE_45:ROUTE, 0.171,R15C15B.Q0,R14C15A.D0,apple_module/rd[5]:CTOF_DEL, 0.101,R14C15A.D0,R14C15A.F0,apple_module/SLICE_54:ROUTE, 0.433,R14C15A.F0,EBR_R13C10.DIA4,apple_module/un1_a_3[0]">Data path</A> apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R15C15B.CLK to R15C15B.Q0 <A href="#@comp:apple_module/SLICE_45">apple_module/SLICE_45</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
|
|
ROUTE 1 0.171<A href="#@net:apple_module/rd[5]:R15C15B.Q0:R14C15A.D0:0.171"> R15C15B.Q0 to R14C15A.D0 </A> <A href="#@net:apple_module/rd[5]">apple_module/rd[5]</A>
|
|
CTOF_DEL --- 0.101 R14C15A.D0 to R14C15A.F0 <A href="#@comp:apple_module/SLICE_54">apple_module/SLICE_54</A>
|
|
ROUTE 2 0.433<A href="#@net:apple_module/un1_a_3[0]:R14C15A.F0:EBR_R13C10.DIA4:0.433"> R14C15A.F0 to EBR_R13C10.DIA4</A> <A href="#@net:apple_module/un1_a_3[0]">apple_module/un1_a_3[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
|
|
--------
|
|
0.838 (27.9% logic, 72.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15B.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_45:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
|
|
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
|
|
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
|
|
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15B.CLK:1.031"> R14C18C.F1 to R15C15B.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
|
|
--------
|
|
3.051 (25.6% logic, 74.4% route), 4 logic levels.
|
|
|
|
Source Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
|
|
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
|
|
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
|
|
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
|
|
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
|
|
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
|
|
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
|
|
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
|
|
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
|
|
--------
|
|
4.527 (21.1% logic, 78.9% route), 5 logic levels.
|
|
|
|
Destination Clock f/b:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
|
|
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
|
|
--------
|
|
0.000 (0.0% logic, 0.0% route), 1 logic levels.
|
|
|
|
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY NET "sys_clock_c" 25.000000 | | |
|
|
MHz ; | -| -| 0
|
|
| | |
|
|
FREQUENCY NET "circuit_clk" 14.285714 | | |
|
|
MHz ; | 0.000 ns| 0.379 ns| 2
|
|
| | |
|
|
FREQUENCY PORT "sys_clock" 25.000000 | | |
|
|
MHz ; | -| -| 2 *
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
1 preference(marked by "*" above) not met.
|
|
|
|
----------------------------------------------------------------------------
|
|
Critical Nets | Loads| Errors| % of total
|
|
----------------------------------------------------------------------------
|
|
apple_module/states[3] | 9| 7| 70.00%
|
|
| | |
|
|
apple_module/un1_a_3[0] | 2| 2| 20.00%
|
|
| | |
|
|
apple_module/un1_a_1[0] | 2| 2| 20.00%
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
|
------------------------
|
|
|
|
Found 8 clocks:
|
|
|
|
Clock Domain: <A href="#@net:apple_module/un1_rda_1">apple_module/un1_rda_1</A> Source: apple_module/SLICE_68.F1 Loads: 1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 27
|
|
|
|
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: <A href="#@net:circuit_clk">circuit_clk</A> Source: clock_module/PLLInst_0.CLKOS
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1 Loads: 16
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: <A href="#@net:apple_module/un1_rda_1">apple_module/un1_rda_1</A> Source: apple_module/SLICE_68.F1 Loads: 1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1 Loads: 16
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 9
|
|
|
|
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
|
|
|
|
Clock Domain: <A href="#@net:apple_module/line_clock">apple_module/line_clock</A> Source: apple_module/SLICE_26.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
|
|
|
|
Clock Domain: <A href="#@net:circuit_clk">circuit_clk</A> Source: clock_module/PLLInst_0.CLKOS
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 5
|
|
|
|
Clock Domain: <A href="#@net:apple_module/line_clock">apple_module/line_clock</A> Source: apple_module/SLICE_26.F1 Loads: 5
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1 Loads: 16
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:apple_module/un1_rda_1">apple_module/un1_rda_1</A> Source: apple_module/SLICE_68.F1
|
|
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
|
|
|
|
Clock Domain: <A href="#@net:circuit_clk">circuit_clk</A> Source: clock_module/PLLInst_0.CLKOS Loads: 26
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:apple_module/line_clock">apple_module/line_clock</A> Source: apple_module/SLICE_26.F1
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 6
|
|
|
|
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
|
|
Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
|
|
|
|
Clock Domain: <A href="#@net:sys_clock_c">sys_clock_c</A> Source: sys_clock.PAD Loads: 1
|
|
No transfer within this clock domain is found
|
|
|
|
|
|
Timing summary (Hold):
|
|
---------------
|
|
|
|
Timing errors: 10 Score: 19900
|
|
Cumulative negative slack: 19900
|
|
|
|
Constraints cover 786 paths, 10 nets, and 594 connections (98.84% coverage)
|
|
|
|
|
|
|
|
Timing summary (Setup and Hold):
|
|
---------------
|
|
|
|
Timing errors: 7 (setup), 10 (hold)
|
|
Score: 76216 (setup), 19900 (hold)
|
|
Cumulative negative slack: 96116 (76216+19900)
|