430 lines
22 KiB
Plaintext
430 lines
22 KiB
Plaintext
#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
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#install: C:\lscc\diamond\3.10_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: MARKF-PRO
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# Tue Feb 27 12:52:06 2018
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.10_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
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@N:"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Top entity is set to FleaFPGA_Uno_E1.
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VHDL syntax check successful!
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@N: CD630 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Synthesizing work.fleafpga_uno_e1.arch.
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@N: CD630 :"C:\Dev\Apple1Display\impl1\source\blinky.vhd":5:7:5:12|Synthesizing work.blinky.behavior.
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Post processing for work.blinky.behavior
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Post processing for work.fleafpga_uno_e1.arch
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Feb 27 12:52:06 2018
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Feb 27 12:52:07 2018
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Feb 27 12:52:07 2018
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Feb 27 12:52:08 2018
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###########################################################]
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Pre-mapping Report
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# Tue Feb 27 12:52:08 2018
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Dev\Apple1Display\impl1\Apple1Display_impl1_scck.rpt
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Printing clock summary report in "C:\Dev\Apple1Display\impl1\Apple1Display_impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=26 set on top level netlist FleaFPGA_Uno_E1
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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--------------------------------------------------------------------------------------------------------------
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0 - FleaFPGA_Uno_E1|sys_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 25
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==============================================================================================================
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@W: MT529 :"c:\dev\apple1display\impl1\source\blinky.vhd":20:6:20:7|Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 25 sequential elements including user_module1.toggle. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 27 12:52:09 2018
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###########################################################]
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Map & Optimize Report
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# Tue Feb 27 12:52:09 2018
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Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Available hyper_sources - for debug and ip models
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None Found
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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1 0h:00m:00s 994.75ns 9 / 25
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 25 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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============================= Non-Gated/Non-Generated Clocks ==============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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-------------------------------------------------------------------------------------------
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@K:CKID0001 sys_clock port 25 user_module1.toggle
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===========================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 141MB)
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Writing Analyst data base C:\Dev\Apple1Display\impl1\synwork\Apple1Display_impl1_m.srm
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Writing EDIF Netlist and constraint files
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@N: FX1056 |Writing EDF file: C:\Dev\Apple1Display\impl1\Apple1Display_impl1.edi
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M-2017.03L-SP1-1
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
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Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
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@W: MT420 |Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 1000.00ns. Please declare a user-defined clock on object "p:sys_clock"
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##### START OF TIMING REPORT #####[
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# Timing Report written on Tue Feb 27 12:52:10 2018
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#
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Top view: FleaFPGA_Uno_E1
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Requested Frequency: 1.0 MHz
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Wire load mode: top
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Paths requested: 5
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Constraint File(s):
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@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
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@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
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Performance Summary
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*******************
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Worst slack in design: 993.759
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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----------------------------------------------------------------------------------------------------------------------------------
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FleaFPGA_Uno_E1|sys_clock 1.0 MHz 160.2 MHz 1000.000 6.241 993.759 inferred Inferred_clkgroup_0
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==================================================================================================================================
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Clock Relationships
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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----------------------------------------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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----------------------------------------------------------------------------------------------------------------------------------------------
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FleaFPGA_Uno_E1|sys_clock FleaFPGA_Uno_E1|sys_clock | 1000.000 993.759 | No paths - | No paths - | No paths -
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==============================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Interface Information
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*********************
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No IO constraint found
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====================================
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Detailed Report for Clock: FleaFPGA_Uno_E1|sys_clock
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Clock
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--------------------------------------------------------------------------------------------------------------
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user_module1.count[5] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[5] 1.044 993.759
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user_module1.count[8] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[8] 1.044 993.759
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user_module1.count[9] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[9] 1.044 993.759
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user_module1.count[10] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[10] 1.044 993.759
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user_module1.count[11] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[11] 1.044 993.759
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user_module1.count[12] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[12] 1.044 993.759
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user_module1.count[13] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[13] 1.044 993.759
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user_module1.count[0] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[0] 1.044 994.186
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user_module1.count[1] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[1] 0.972 994.401
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user_module1.count[2] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q count[2] 0.972 994.401
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==============================================================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Clock
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----------------------------------------------------------------------------------------------------------------
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user_module1.count[0] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[1] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[2] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[3] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[4] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[5] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[6] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[7] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[8] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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user_module1.count[9] FleaFPGA_Uno_E1|sys_clock FD1S3IX CD un2_count_i 999.197 993.759
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================================================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 1000.000
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- Setup time: 0.803
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 999.197
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- Propagation time: 5.438
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : 993.759
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Number of logic level(s): 4
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Starting point: user_module1.count[5] / Q
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Ending point: user_module1.count[0] / CD
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The start point is clocked by FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
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The end point is clocked by FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------
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user_module1.count[5] FD1S3IX Q Out 1.044 1.044 -
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count[5] Net - - - - 2
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user_module1.un2_countlto9_2 ORCALUT4 A In 0.000 1.044 -
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user_module1.un2_countlto9_2 ORCALUT4 Z Out 1.017 2.061 -
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un2_countlto9_2 Net - - - - 1
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user_module1.un2_countlto13 ORCALUT4 C In 0.000 2.061 -
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user_module1.un2_countlto13 ORCALUT4 Z Out 1.017 3.077 -
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un2_countlt14 Net - - - - 1
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user_module1.un2_countlto16 ORCALUT4 D In 0.000 3.077 -
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user_module1.un2_countlto16 ORCALUT4 Z Out 1.017 4.094 -
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un2_countlt21 Net - - - - 1
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user_module1.un2_countlto21_3_RNIB53I ORCALUT4 C In 0.000 4.094 -
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user_module1.un2_countlto21_3_RNIB53I ORCALUT4 Z Out 1.344 5.438 -
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un2_count_i Net - - - - 25
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user_module1.count[0] FD1S3IX CD In 0.000 5.438 -
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========================================================================================================
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##### END OF TIMING REPORT #####]
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Timing exceptions that could not be applied
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None
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Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
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Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
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---------------------------------------
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Resource Usage Report
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Part: lcmxo2_7000hc-4
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Register bits: 25 of 6864 (0%)
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PIC Latch: 0
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I/O cells: 11
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Details:
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CCU2D: 13
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FD1S3AY: 1
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FD1S3IX: 24
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GSR: 1
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IB: 1
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INV: 1
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OB: 10
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ORCALUT4: 8
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PUR: 1
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VHI: 2
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VLO: 2
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 27 12:52:10 2018
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###########################################################]
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