643 lines
40 KiB
Plaintext
643 lines
40 KiB
Plaintext
#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
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#install: C:\lscc\diamond\3.10_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: MARKF-PRO
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# Wed Oct 10 17:24:41 2018
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.10_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
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@N:"C:\dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Top entity is set to FleaFPGA_Uno_E1.
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Options changed - recompiling
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@W: CD433 :"C:\dev\Apple1Display\ttl\dm74166.vhd":1:9:1:9|No design units in file
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@W: CD433 :"C:\dev\Apple1Display\ttl\dm74174.vhd":1:9:1:9|No design units in file
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@W: CD433 :"C:\dev\Apple1Display\ttl\2504.vhd":1:9:1:9|No design units in file
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@W: CD433 :"C:\dev\Apple1Display\ttl\2519.vhd":1:9:1:9|No design units in file
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VHDL syntax check successful!
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Options changed - recompiling
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@N: CD630 :"C:\dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Synthesizing work.fleafpga_uno_e1.arch.
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@N: CD630 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":5:7:5:19|Synthesizing work.apple1display.behavior.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":44:14:44:25|Port q2_i of entity work.dm74175 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":44:14:44:25|Port q3_i of entity work.dm74175 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":44:14:44:25|Port q0 of entity work.dm74175 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":44:14:44:25|Port q1 of entity work.dm74175 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":44:14:44:25|Port q2 of entity work.dm74175 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":44:14:44:25|Port q3 of entity work.dm74175 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":146:14:146:24|Port y2 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":146:14:146:24|Port y1 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":146:14:146:24|Port y0 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":155:14:155:24|Port y4 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":155:14:155:24|Port y2 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":155:14:155:24|Port y1 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":155:14:155:24|Port y0 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":166:14:166:24|Port y3 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":166:14:166:24|Port y1 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\dev\Apple1Display\impl1\Apple1Display.vhd":166:14:166:24|Port y0 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@N: CD630 :"C:\dev\Apple1Display\ttl\dm7400.vhd":6:7:6:12|Synthesizing work.dm7400.behavior.
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Post processing for work.dm7400.behavior
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@N: CD630 :"C:\dev\Apple1Display\ttl\dm7404.vhd":6:7:6:12|Synthesizing work.dm7404.behavior.
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Post processing for work.dm7404.behavior
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@N: CD630 :"C:\dev\Apple1Display\ttl\dm7402.vhd":6:7:6:12|Synthesizing work.dm7402.behavior.
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Post processing for work.dm7402.behavior
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@N: CD630 :"C:\dev\Apple1Display\ttl\dm74161.vhd":6:7:6:13|Synthesizing work.dm74161.behavior.
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Post processing for work.dm74161.behavior
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@N: CD630 :"C:\dev\Apple1Display\ttl\dm74160.vhd":6:7:6:13|Synthesizing work.dm74160.behavior.
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Post processing for work.dm74160.behavior
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@N: CD630 :"C:\dev\Apple1Display\ttl\dm74175.vhd":8:7:8:13|Synthesizing work.dm74175.behavior.
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Post processing for work.dm74175.behavior
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Post processing for work.apple1display.behavior
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@N: CD630 :"C:\dev\Apple1Display\impl1\divider.vhd":5:7:5:13|Synthesizing work.divider.behavior.
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Post processing for work.divider.behavior
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@N: CD630 :"C:\dev\Apple1Display\impl1\master_clk.vhd":14:7:14:16|Synthesizing work.master_clk.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":2221:10:2221:16|Synthesizing work.ehxpllj.syn_black_box.
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Post processing for work.ehxpllj.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1490:10:1490:12|Synthesizing work.vlo.syn_black_box.
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Post processing for work.vlo.syn_black_box
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Post processing for work.master_clk.structure
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Post processing for work.fleafpga_uno_e1.arch
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Oct 10 17:24:42 2018
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Oct 10 17:24:42 2018
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Oct 10 17:24:42 2018
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Oct 10 17:24:43 2018
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###########################################################]
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Pre-mapping Report
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# Wed Oct 10 17:24:44 2018
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@A: MF827 |No constraint file specified.
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@L: C:\dev\Apple1Display\impl1\impl1_scck.rpt
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Printing clock summary report in "C:\dev\Apple1Display\impl1\impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@N: BN115 :"c:\dev\apple1display\impl1\apple1display.vhd":146:14:146:24|Removing instance C10 (in view: work.apple1display(behavior)) of type view:work.dm7402(behavior) because it does not drive other instances.
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=26 set on top level netlist FleaFPGA_Uno_E1
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
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0 - dm74175|q0_i_inferred_clock 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_1 5
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1 . dm74161_4|count_derived_clock[3] 1.0 MHz 1000.000 derived (from dm74175|q0_i_inferred_clock) Autoconstr_clkgroup_1 20
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0 - master_clk|CLKOP_inferred_clock 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 4
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1 . divider|toggle_derived_clock 1.0 MHz 1000.000 derived (from master_clk|CLKOP_inferred_clock) Autoconstr_clkgroup_0 4
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===============================================================================================================================================================
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@W: MT529 :"c:\dev\apple1display\impl1\divider.vhd":21:6:21:7|Found inferred clock master_clk|CLKOP_inferred_clock which controls 4 sequential elements including div_module.toggle. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":26:2:26:3|Found inferred clock dm74175|q0_i_inferred_clock which controls 5 sequential elements including apple_module.C13.states[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Wed Oct 10 17:24:44 2018
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###########################################################]
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Map & Optimize Report
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# Wed Oct 10 17:24:44 2018
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Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: BN362 :"c:\dev\apple1display\ttl\dm74175.vhd":26:2:26:3|Removing sequential instance states[2] (in view: work.dm74175(behavior)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"c:\dev\apple1display\ttl\dm74175.vhd":26:2:26:3|Removing sequential instance states[3] (in view: work.dm74175(behavior)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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Available hyper_sources - for debug and ip models
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None Found
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@N: MT206 |Auto Constrain mode is enabled
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@N: FX493 |Applying initial value "0000" on instance apple_module.C13.states[3:0].
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: MO231 :"c:\dev\apple1display\ttl\dm74160.vhd":24:2:24:3|Found counter in view:work.apple1display(behavior) instance D6.count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":24:2:24:3|Found counter in view:work.dm74161_3(behavior) instance count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":24:2:24:3|Found counter in view:work.dm74161_2(behavior) instance count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":24:2:24:3|Found counter in view:work.dm74161_1(behavior) instance count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":24:2:24:3|Found counter in view:work.dm74161_0(behavior) instance count[3:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)
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Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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@N: FA113 :"c:\dev\apple1display\impl1\divider.vhd":22:13:22:29|Pipelining module un2_count. For more information, search for "pipelining" in Online Help.
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@N: MF169 :"c:\dev\apple1display\impl1\divider.vhd":21:6:21:7|Pushed in register count[2:0].
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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1 0h:00m:00s -1.81ns 53 / 31
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2 0h:00m:00s -1.84ns 74 / 31
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3 0h:00m:00s -1.84ns 63 / 31
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@N: FX271 :"c:\dev\apple1display\ttl\dm74160.vhd":24:2:24:3|Replicating instance apple_module.D6.count[0] (in view: work.FleaFPGA_Uno_E1(arch)) with 8 loads 1 time to improve timing.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74160.vhd":24:2:24:3|Replicating instance apple_module.D6.count[1] (in view: work.FleaFPGA_Uno_E1(arch)) with 6 loads 1 time to improve timing.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74160.vhd":24:2:24:3|Replicating instance apple_module.D6.count[2] (in view: work.FleaFPGA_Uno_E1(arch)) with 7 loads 1 time to improve timing.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74160.vhd":24:2:24:3|Replicating instance apple_module.D6.count[3] (in view: work.FleaFPGA_Uno_E1(arch)) with 6 loads 1 time to improve timing.
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Timing driven replication report
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Added 4 Registers via timing driven replication
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Added 4 LUTs via timing driven replication
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4 0h:00m:00s -1.40ns 72 / 35
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5 0h:00m:00s -1.33ns 72 / 35
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6 0h:00m:00s -1.33ns 71 / 35
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
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@N: MT611 :|Automatically generated clock divider|toggle_derived_clock is not used and is being removed
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@N: MT611 :|Automatically generated clock dm74175|q0_i_inferred_clock is not used and is being removed
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@N: MT617 :|Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
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1 gated/generated clock tree(s) driving 35 clock pin(s) of sequential element(s)
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0 instances converted, 35 sequential instances remain driven by gated/generated clocks
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|
====================================================================================================== Gated/Generated Clocks =======================================================================================================
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|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
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|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
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@K:CKID0001 clock_module.PLLInst_0 EHXPLLJ 35 div_module.count[2] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
|
|
=====================================================================================================================================================================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 142MB)
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Writing Analyst data base C:\dev\Apple1Display\impl1\synwork\impl1_m.srm
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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|
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Writing EDIF Netlist and constraint files
|
|
@N: FX1056 |Writing EDF file: C:\dev\Apple1Display\impl1\impl1.edi
|
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M-2017.03L-SP1-1
|
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
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Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
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@W: MT246 :"c:\dev\apple1display\impl1\master_clk.vhd":104:4:104:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
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@W: MT420 |Found inferred clock master_clk|CLKOP_inferred_clock with period 4.32ns. Please declare a user-defined clock on object "n:clock_module.CLKOP"
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##### START OF TIMING REPORT #####[
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# Timing Report written on Wed Oct 10 17:24:46 2018
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#
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Top view: FleaFPGA_Uno_E1
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Requested Frequency: 231.3 MHz
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Wire load mode: top
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Paths requested: 5
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Constraint File(s):
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@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
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@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
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Performance Summary
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*******************
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Worst slack in design: -0.579
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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-----------------------------------------------------------------------------------------------------------------------------------------
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master_clk|CLKOP_inferred_clock 231.3 MHz 204.0 MHz 4.323 4.902 -0.579 inferred Autoconstr_clkgroup_0
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System 1.0 MHz NA 1000.000 NA NA system system_clkgroup
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=========================================================================================================================================
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Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
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Clock Relationships
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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---------------------------------------------------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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---------------------------------------------------------------------------------------------------------------------------------------------------------
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master_clk|CLKOP_inferred_clock master_clk|CLKOP_inferred_clock | 4.323 -0.579 | No paths - | No paths - | No paths -
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=========================================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Interface Information
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*********************
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No IO constraint found
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====================================
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Detailed Report for Clock: master_clk|CLKOP_inferred_clock
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
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------------------------------------------------------------------------------------------------------------------------------------
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apple_module.D6.count[1] master_clk|CLKOP_inferred_clock FD1P3AX Q count[1] 1.204 -0.579
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apple_module.D6.count[3] master_clk|CLKOP_inferred_clock FD1P3AX Q count[3] 1.180 -0.555
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apple_module.D6.count[2] master_clk|CLKOP_inferred_clock FD1P3AX Q count[2] 1.204 -0.067
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apple_module.D9.count[0] master_clk|CLKOP_inferred_clock FD1S3DX Q count[0] 1.180 0.013
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apple_module.D8.count[3] master_clk|CLKOP_inferred_clock FD1S3DX Q count[3] 1.180 0.013
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apple_module.D6.count_fast[0] master_clk|CLKOP_inferred_clock FD1P3AX Q count_fast[0] 1.108 0.029
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apple_module.D9.count[1] master_clk|CLKOP_inferred_clock FD1S3DX Q count[1] 1.148 0.045
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apple_module.D6.count_fast[1] master_clk|CLKOP_inferred_clock FD1P3AX Q count_fast[1] 1.044 0.334
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apple_module.D6.count_fast[3] master_clk|CLKOP_inferred_clock FD1P3AX Q count_fast[3] 1.044 0.334
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apple_module.D7.count[3] master_clk|CLKOP_inferred_clock FD1S3AX Q horz_count_upper[3] 1.252 0.390
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====================================================================================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
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-------------------------------------------------------------------------------------------------------------------------
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apple_module.D15.count[0] master_clk|CLKOP_inferred_clock FD1P3AX SP g0 3.851 -0.579
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apple_module.D15.count[1] master_clk|CLKOP_inferred_clock FD1P3AX SP g0 3.851 -0.579
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apple_module.D15.count[2] master_clk|CLKOP_inferred_clock FD1P3AX SP g0 3.851 -0.579
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apple_module.D15.count[3] master_clk|CLKOP_inferred_clock FD1P3AX SP g0 3.851 -0.579
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apple_module.D8.count[0] master_clk|CLKOP_inferred_clock FD1S3DX D counte_0[0] 4.412 -0.067
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apple_module.D8.count[1] master_clk|CLKOP_inferred_clock FD1S3DX D counte_0[1] 4.412 -0.067
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apple_module.D8.count[2] master_clk|CLKOP_inferred_clock FD1S3DX D counte_0[2] 4.412 -0.067
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apple_module.D8.count[3] master_clk|CLKOP_inferred_clock FD1S3DX D counte_0[3] 4.412 -0.067
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apple_module.D9.count[0] master_clk|CLKOP_inferred_clock FD1S3DX D counte_0[0] 4.412 0.270
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apple_module.D7.count[0] master_clk|CLKOP_inferred_clock FD1S3AX D counte_0[0] 4.412 0.270
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=========================================================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 4.323
|
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- Setup time: 0.472
|
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 3.851
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- Propagation time: 4.430
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -0.579
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Number of logic level(s): 3
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Starting point: apple_module.D6.count[1] / Q
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Ending point: apple_module.D15.count[0] / SP
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The start point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
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The end point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------
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apple_module.D6.count[1] FD1P3AX Q Out 1.204 1.204 -
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count[1] Net - - - - 7
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apple_module.D15.g3_0_0 ORCALUT4 A In 0.000 1.204 -
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apple_module.D15.g3_0_0 ORCALUT4 Z Out 1.017 2.221 -
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g3_0_0_0 Net - - - - 1
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apple_module.D15.g3_0_3 ORCALUT4 B In 0.000 2.221 -
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apple_module.D15.g3_0_3 ORCALUT4 Z Out 1.017 3.237 -
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g3_0_3 Net - - - - 1
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apple_module.D15.g0 ORCALUT4 C In 0.000 3.237 -
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apple_module.D15.g0 ORCALUT4 Z Out 1.193 4.430 -
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g0 Net - - - - 4
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apple_module.D15.count[0] FD1P3AX SP In 0.000 4.430 -
|
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============================================================================================
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Path information for path number 2:
|
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Requested Period: 4.323
|
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- Setup time: 0.472
|
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+ Clock delay at ending point: 0.000 (ideal)
|
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= Required time: 3.851
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|
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- Propagation time: 4.430
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -0.579
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Number of logic level(s): 3
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Starting point: apple_module.D6.count[1] / Q
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Ending point: apple_module.D15.count[3] / SP
|
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The start point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
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The end point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
|
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--------------------------------------------------------------------------------------------
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apple_module.D6.count[1] FD1P3AX Q Out 1.204 1.204 -
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count[1] Net - - - - 7
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apple_module.D15.g3_0_0 ORCALUT4 A In 0.000 1.204 -
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apple_module.D15.g3_0_0 ORCALUT4 Z Out 1.017 2.221 -
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g3_0_0_0 Net - - - - 1
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apple_module.D15.g3_0_3 ORCALUT4 B In 0.000 2.221 -
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apple_module.D15.g3_0_3 ORCALUT4 Z Out 1.017 3.237 -
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g3_0_3 Net - - - - 1
|
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apple_module.D15.g0 ORCALUT4 C In 0.000 3.237 -
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apple_module.D15.g0 ORCALUT4 Z Out 1.193 4.430 -
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g0 Net - - - - 4
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apple_module.D15.count[3] FD1P3AX SP In 0.000 4.430 -
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============================================================================================
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|
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Path information for path number 3:
|
|
Requested Period: 4.323
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.851
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|
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- Propagation time: 4.430
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : -0.579
|
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|
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Number of logic level(s): 3
|
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Starting point: apple_module.D6.count[1] / Q
|
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Ending point: apple_module.D15.count[2] / SP
|
|
The start point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
|
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The end point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
|
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Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------
|
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apple_module.D6.count[1] FD1P3AX Q Out 1.204 1.204 -
|
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count[1] Net - - - - 7
|
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apple_module.D15.g3_0_0 ORCALUT4 A In 0.000 1.204 -
|
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apple_module.D15.g3_0_0 ORCALUT4 Z Out 1.017 2.221 -
|
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g3_0_0_0 Net - - - - 1
|
|
apple_module.D15.g3_0_3 ORCALUT4 B In 0.000 2.221 -
|
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apple_module.D15.g3_0_3 ORCALUT4 Z Out 1.017 3.237 -
|
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g3_0_3 Net - - - - 1
|
|
apple_module.D15.g0 ORCALUT4 C In 0.000 3.237 -
|
|
apple_module.D15.g0 ORCALUT4 Z Out 1.193 4.430 -
|
|
g0 Net - - - - 4
|
|
apple_module.D15.count[2] FD1P3AX SP In 0.000 4.430 -
|
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============================================================================================
|
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|
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|
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Path information for path number 4:
|
|
Requested Period: 4.323
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.851
|
|
|
|
- Propagation time: 4.430
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : -0.579
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.D6.count[1] / Q
|
|
Ending point: apple_module.D15.count[1] / SP
|
|
The start point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
|
|
The end point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------
|
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apple_module.D6.count[1] FD1P3AX Q Out 1.204 1.204 -
|
|
count[1] Net - - - - 7
|
|
apple_module.D15.g3_0_0 ORCALUT4 A In 0.000 1.204 -
|
|
apple_module.D15.g3_0_0 ORCALUT4 Z Out 1.017 2.221 -
|
|
g3_0_0_0 Net - - - - 1
|
|
apple_module.D15.g3_0_3 ORCALUT4 B In 0.000 2.221 -
|
|
apple_module.D15.g3_0_3 ORCALUT4 Z Out 1.017 3.237 -
|
|
g3_0_3 Net - - - - 1
|
|
apple_module.D15.g0 ORCALUT4 C In 0.000 3.237 -
|
|
apple_module.D15.g0 ORCALUT4 Z Out 1.193 4.430 -
|
|
g0 Net - - - - 4
|
|
apple_module.D15.count[1] FD1P3AX SP In 0.000 4.430 -
|
|
============================================================================================
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 4.323
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.851
|
|
|
|
- Propagation time: 4.406
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.555
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.D6.count[3] / Q
|
|
Ending point: apple_module.D15.count[0] / SP
|
|
The start point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
|
|
The end point is clocked by master_clk|CLKOP_inferred_clock [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------
|
|
apple_module.D6.count[3] FD1P3AX Q Out 1.180 1.180 -
|
|
count[3] Net - - - - 5
|
|
apple_module.D15.g3_0_0 ORCALUT4 B In 0.000 1.180 -
|
|
apple_module.D15.g3_0_0 ORCALUT4 Z Out 1.017 2.197 -
|
|
g3_0_0_0 Net - - - - 1
|
|
apple_module.D15.g3_0_3 ORCALUT4 B In 0.000 2.197 -
|
|
apple_module.D15.g3_0_3 ORCALUT4 Z Out 1.017 3.213 -
|
|
g3_0_3 Net - - - - 1
|
|
apple_module.D15.g0 ORCALUT4 C In 0.000 3.213 -
|
|
apple_module.D15.g0 ORCALUT4 Z Out 1.193 4.406 -
|
|
g0 Net - - - - 4
|
|
apple_module.D15.count[0] FD1P3AX SP In 0.000 4.406 -
|
|
============================================================================================
|
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
|
|
|
Timing exceptions that could not be applied
|
|
None
|
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
|
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
|
|
|
|
---------------------------------------
|
|
Resource Usage Report
|
|
Part: lcmxo2_7000hc-4
|
|
|
|
Register bits: 35 of 6864 (1%)
|
|
PIC Latch: 0
|
|
I/O cells: 13
|
|
|
|
|
|
Details:
|
|
FD1P3AX: 17
|
|
FD1S3AX: 10
|
|
FD1S3DX: 8
|
|
GSR: 1
|
|
IB: 1
|
|
INV: 2
|
|
OB: 12
|
|
ORCALUT4: 63
|
|
PUR: 1
|
|
VHI: 12
|
|
VLO: 12
|
|
Mapper successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 32MB peak: 146MB)
|
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
|
# Wed Oct 10 17:24:46 2018
|
|
|
|
###########################################################]
|