34 lines
601 B
VHDL
34 lines
601 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity divider is
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generic(div : natural := 2);
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port(
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input: in std_logic;
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output: out std_logic);
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end divider;
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architecture behavior OF divider IS
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signal toggle : std_logic := '0';
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begin
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process(input)
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variable count : integer range 0 to (div/2)-1 := 0;
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begin
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if rising_edge(input) then
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if count /= 0 then
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count := count - 1;
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else
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count := (div/2)-1;
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toggle <= not toggle;
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end if;
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end if;
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end process;
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output <= toggle;
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end architecture;
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