42 lines
3.6 KiB
Plaintext
42 lines
3.6 KiB
Plaintext
# Synopsys Constraint Checker(syntax only), version maplat, Build 1796R, built Aug 4 2017
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# Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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# Written on Thu Aug 8 18:40:12 2019
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##### DESIGN INFO #######################################################
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Top View: "FleaFPGA_Uno_E1"
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Constraint File(s): (none)
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#Run constraint checker to find more issues with constraints.
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#########################################################################
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No issues found in constraint syntax.
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Clock Summary
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*************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------------------------------------------------------------------
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0 - System 1.0 MHz 1000.000 system system_clkgroup 0
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0 - dm7427|y1_inferred_clock 259.2 MHz 3.858 inferred Autoconstr_clkgroup_3 83
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0 - FleaFPGA_Uno_E1|sys_clock 236.1 MHz 4.236 inferred Autoconstr_clkgroup_0 57
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0 - dm7400_1|y3_inferred_clock 483.5 MHz 2.068 inferred Autoconstr_clkgroup_2 44
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0 - dm74175|q0_i_inferred_clock 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_5 13
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1 . dm74161_4|count_derived_clock[3] 1.0 MHz 1000.000 derived (from dm74175|q0_i_inferred_clock) Autoconstr_clkgroup_5 21
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0 - dm7400_1|y1_inferred_clock 329.3 MHz 3.037 inferred Autoconstr_clkgroup_4 7
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0 - master_clk|CLKOS_inferred_clock 285.4 MHz 3.504 inferred Autoconstr_clkgroup_1 6
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===========================================================================================================================================================
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