108 lines
3.3 KiB
Plaintext
108 lines
3.3 KiB
Plaintext
#-- Synopsys, Inc.
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#-- Version M-2017.03L-SP1-1
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#-- Project file C:\Dev\Apple1Display\impl1\impl1_syn.prj
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#-- Written on Thu Aug 8 18:39:46 2019
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#project files
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add_file -vhdl -lib work "C:/lscc/diamond/3.10_x64/cae_library/synthesis/vhdl/machxo2.vhd"
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add_file -vhdl -lib work "source/FleaFPGA_Uno_Top.vhd"
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add_file -vhdl -lib work "Apple1Display.vhd"
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add_file -vhdl -lib work "source/ntsc.vhd"
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add_file -vhdl -lib work "divider.vhd"
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add_file -vhdl -lib work "master_clk.vhd"
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add_file -vhdl -lib work "../ttl/dm7400.vhd"
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add_file -vhdl -lib work "../ttl/dm7402.vhd"
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add_file -vhdl -lib work "../ttl/dm7404.vhd"
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add_file -vhdl -lib work "../ttl/dm7408.vhd"
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add_file -vhdl -lib work "../ttl/dm7410.vhd"
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add_file -vhdl -lib work "../ttl/dm7427.vhd"
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add_file -vhdl -lib work "../ttl/dm7432.vhd"
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add_file -vhdl -lib work "../ttl/dm7450.vhd"
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add_file -vhdl -lib work "../ttl/dm74157.vhd"
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add_file -vhdl -lib work "../ttl/dm74160.vhd"
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add_file -vhdl -lib work "../ttl/dm74161.vhd"
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add_file -vhdl -lib work "../ttl/dm74166.vhd"
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add_file -vhdl -lib work "../ttl/dm74174.vhd"
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add_file -vhdl -lib work "../ttl/dm74175.vhd"
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add_file -vhdl -lib work "../ttl/2504.vhd"
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add_file -vhdl -lib work "../ttl/2519.vhd"
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add_file -vhdl -lib work "../ttl/dm2513.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/CharacterRom.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/ScreenRom.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/ShiftReg40.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/test_entity.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/ShiftReg1024.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/ScreenRom2.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/ScreenRam.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/CursorRam.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/UART_RX.vhd"
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add_file -vhdl -lib work "../ttl/ne555.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/sig2504.vhd"
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add_file -vhdl -lib work "C:/Dev/Apple1Display/sig2513.vhd"
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#implementation: "impl1"
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impl -add impl1 -type fpga
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#
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#implementation attributes
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set_option -vlog_std sysv
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set_option -project_relative_includes 1
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#device options
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set_option -technology MACHXO2
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set_option -part LCMXO2_7000HC
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set_option -package TG144C
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set_option -speed_grade -4
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set_option -part_companion ""
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#compilation/mapping options
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set_option -top_module "FleaFPGA_Uno_E1"
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# hdl_compiler_options
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set_option -distributed_compile 0
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# mapper_without_write_options
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set_option -frequency auto
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set_option -srs_instrumentation 1
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# mapper_options
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set_option -write_verilog 0
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set_option -write_vhdl 0
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# Lattice XP
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set_option -maxfan 1000
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set_option -disable_io_insertion 0
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set_option -retiming 0
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set_option -pipe 1
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set_option -forcegsr no
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set_option -fix_gated_and_generated_clocks 1
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set_option -rw_check_on_ram 1
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set_option -update_models_cp 0
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set_option -syn_edif_array_rename 1
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set_option -Write_declared_clocks_only 1
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# NFilter
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set_option -no_sequential_opt 0
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# sequential_optimization_options
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set_option -symbolic_fsm_compiler 1
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# Compiler Options
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set_option -compiler_compatible 0
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set_option -resource_sharing 1
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set_option -multi_file_compilation_unit 1
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# Compiler Options
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set_option -auto_infer_blackbox 0
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "./impl1.edi"
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impl -active "impl1"
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