27 lines
1.2 KiB
Plaintext
27 lines
1.2 KiB
Plaintext
SCUBA, Version Diamond (64-bit) 3.10.2.115
|
|
Mon Aug 05 08:34:49 2019
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
Issued command : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n master_clk -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 25 -fclkop_tol 0.0 -fclkos 14.31818 -fclkos_tol 0.5 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 5
|
|
Circuit name : master_clk
|
|
Module type : pll
|
|
Module Version : 5.7
|
|
Ports :
|
|
Inputs : CLKI
|
|
Outputs : CLKOP, CLKOS
|
|
I/O buffer : not inserted
|
|
EDIF output : master_clk.edn
|
|
VHDL output : master_clk.vhd
|
|
VHDL template : master_clk_tmpl.vhd
|
|
VHDL purpose : for synthesis and simulation
|
|
Bus notation : big endian
|
|
Report output : master_clk.srp
|
|
Element Usage :
|
|
EHXPLLJ : 1
|
|
Estimated Resource Usage:
|