93 lines
1.6 KiB
VHDL
93 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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-- NTSC composite DAC output voltages
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-- 0000 -> 0.00V
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-- 0001 -> 0.07V
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-- 0010 -> 0.15V
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-- 0011 -> 0.22V
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-- 0100 -> 0.30V
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-- 0101 -> 0.38V
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-- 0110 -> 0.45V
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-- 0111 -> 0.52V
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-- 1000 -> 0.60V
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-- 1001 -> 0.68V
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-- 1010 -> 0.75V
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-- 1011 -> 0.83V
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-- 1100 -> 0.91V
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-- 1101 -> 0.98V
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-- 1110 -> 1.05V
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-- 1111 -> 1.13V
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entity ntsc is
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port(
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clk: in std_logic;
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ntsc: out std_logic_vector(3 downto 0)
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);
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end ntsc;
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architecture behavior OF ntsc IS
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constant HORZ_RES: natural := 1587; -- 1587
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constant VERT_RES: natural := 525; -- 525
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signal hsync : std_logic := '0';
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signal vsync : std_logic := '0';
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signal image : std_logic := '0';
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signal sync : std_logic;
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begin
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process(clk)
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variable hcount : integer range 0 to HORZ_RES-1 := 0;
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variable vcount : integer range 0 to VERT_RES-1 := 0;
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variable dot_clock : std_logic := '0';
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begin
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if rising_edge(clk) then
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if dot_clock = '0' then
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if (hcount < HORZ_RES-1) then
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hcount := hcount + 1;
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else
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-- new line
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hcount := 0;
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if (vcount < VERT_RES-1) then
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vcount := vcount + 1;
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else
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vcount := 0;
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end if;
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end if;
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end if;
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dot_clock := not dot_clock;
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if (hcount > 0) then
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hsync <= '1';
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else
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hsync <= '0';
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end if;
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if (vcount = 0) then
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vsync <= '1';
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else
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vsync <= '0';
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end if;
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if (vcount > 0) and (hcount = 2) then
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image <= '1';
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else
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image <= '0';
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end if;
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end if;
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end process;
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sync <= vsync or hsync;
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ntsc(0) <= sync;
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ntsc(1) <= image;
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ntsc(2) <= sync;
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ntsc(3) <= image;
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end architecture;
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