168 lines
15 KiB
Plaintext
168 lines
15 KiB
Plaintext
Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.10_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
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@N:"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Top entity is set to FleaFPGA_Uno_E1.
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Options changed - recompiling
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@W: CD433 :"C:\Dev\Apple1Display\ttl\2504.vhd":1:9:1:9|No design units in file
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VHDL syntax check successful!
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Options changed - recompiling
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@N: CD630 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Synthesizing work.fleafpga_uno_e1.arch.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":122:23:122:37|Port clkop of entity work.master_clk is unconnected. If a port needs to remain unconnected, use the keyword open.
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@N: CD630 :"C:\Dev\Apple1Display\UART_RX.vhd":18:7:18:13|Synthesizing work.uart_rx.rtl.
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@N: CD231 :"C:\Dev\Apple1Display\UART_RX.vhd":33:17:33:18|Using onehot encoding for type t_sm_main. For example, enumeration s_idle is mapped to "10000".
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@N: CD604 :"C:\Dev\Apple1Display\UART_RX.vhd":132:8:132:21|OTHERS clause is not synthesized.
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Post processing for work.uart_rx.rtl
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@N: CD630 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":7:7:7:19|Synthesizing work.apple1display.behavior.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":191:13:191:24|Port carry of entity work.dm74161 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":226:14:226:24|Port y2 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":226:14:226:24|Port y1 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|Port y5 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|Port y3 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|Port y2 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":241:14:241:24|Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q0_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q1_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q2_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q3_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q4_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|Port q5_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":354:12:355:4|Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":367:13:368:4|Port y4 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":367:13:368:4|Port y1 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":374:12:375:4|Port y3 of entity work.dm7432 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":381:12:382:4|Port y3 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":381:12:382:4|Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|Port y2 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD326 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|Port y1 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:7:47:22|Signal buffer_char_in_0 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:25:47:40|Signal buffer_char_in_1 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:43:47:58|Signal buffer_char_in_2 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:61:47:76|Signal buffer_char_in_3 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:79:47:94|Signal buffer_char_in_4 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:97:47:112|Signal buffer_char_in_5 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":65:7:65:19|Signal unconnected_1 is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":80:7:80:16|Signal cross_talk is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7400.vhd":6:7:6:12|Synthesizing work.dm7400.behavior.
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Post processing for work.dm7400.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7410.vhd":6:7:6:12|Synthesizing work.dm7410.behavior.
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Post processing for work.dm7410.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7432.vhd":6:7:6:12|Synthesizing work.dm7432.behavior.
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Post processing for work.dm7432.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7408.vhd":6:7:6:12|Synthesizing work.dm7408.behavior.
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Post processing for work.dm7408.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7450.vhd":6:7:6:12|Synthesizing work.dm7450.behavior.
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Post processing for work.dm7450.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7427.vhd":6:7:6:12|Synthesizing work.dm7427.behavior.
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Post processing for work.dm7427.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\ne555.vhd":7:7:7:11|Synthesizing work.ne555.behavior.
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Post processing for work.ne555.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74174.vhd":8:7:8:13|Synthesizing work.dm74174.behavior.
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Post processing for work.dm74174.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74157.vhd":6:7:6:13|Synthesizing work.dm74157.behavior.
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Post processing for work.dm74157.behavior
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@N: CD630 :"C:\Dev\Apple1Display\sig2504.vhd":14:7:14:13|Synthesizing work.sig2504.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1407:10:1407:17|Synthesizing work.rom16x1a.syn_black_box.
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Post processing for work.rom16x1a.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1699:10:1699:14|Synthesizing work.dp8kc.syn_black_box.
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Post processing for work.dp8kc.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":246:10:246:16|Synthesizing work.fd1p3ix.syn_black_box.
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Post processing for work.fd1p3ix.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":167:10:167:12|Synthesizing work.cu2.syn_black_box.
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Post processing for work.cu2.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":177:10:177:15|Synthesizing work.fadd2b.syn_black_box.
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Post processing for work.fadd2b.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1483:10:1483:12|Synthesizing work.vhi.syn_black_box.
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Post processing for work.vhi.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1490:10:1490:12|Synthesizing work.vlo.syn_black_box.
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Post processing for work.vlo.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":681:10:681:12|Synthesizing work.inv.syn_black_box.
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Post processing for work.inv.syn_black_box
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1276:10:1276:12|Synthesizing work.or2.syn_black_box.
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Post processing for work.or2.syn_black_box
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Post processing for work.sig2504.structure
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@N: CD630 :"C:\Dev\Apple1Display\ttl\2519.vhd":8:7:8:13|Synthesizing work.ttl2519.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ShiftReg40.vhd":14:7:14:16|Synthesizing work.shiftreg40.structure.
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Post processing for work.shiftreg40.structure
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Post processing for work.ttl2519.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7404.vhd":6:7:6:12|Synthesizing work.dm7404.behavior.
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Post processing for work.dm7404.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7402.vhd":6:7:6:12|Synthesizing work.dm7402.behavior.
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Post processing for work.dm7402.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74166.vhd":6:7:6:13|Synthesizing work.dm74166.behavior.
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Post processing for work.dm74166.behavior
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@N: CD630 :"C:\Dev\Apple1Display\sig2513.vhd":14:7:14:13|Synthesizing work.sig2513.structure.
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Post processing for work.sig2513.structure
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74161.vhd":6:7:6:13|Synthesizing work.dm74161.behavior.
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Post processing for work.dm74161.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74160.vhd":6:7:6:13|Synthesizing work.dm74160.behavior.
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Post processing for work.dm74160.behavior
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74175.vhd":8:7:8:13|Synthesizing work.dm74175.behavior.
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Post processing for work.dm74175.behavior
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Post processing for work.apple1display.behavior
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:97:47:112|Signal buffer_char_in_5 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:79:47:94|Signal buffer_char_in_4 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:61:47:76|Signal buffer_char_in_3 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:43:47:58|Signal buffer_char_in_2 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:25:47:40|Signal buffer_char_in_1 is floating; a simulation mismatch is possible.
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@W: CL240 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:7:47:22|Signal buffer_char_in_0 is floating; a simulation mismatch is possible.
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":272:15:272:26|Input din of instance D14b is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":271:15:271:26|Input din of instance D14a is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":270:14:270:25|Input din of instance D4b is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":269:14:269:25|Input din of instance D4a is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":268:14:268:25|Input din of instance D5b is floating
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@W: CL167 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":267:14:267:25|Input din of instance D5a is floating
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@N: CD630 :"C:\Dev\Apple1Display\impl1\master_clk.vhd":14:7:14:16|Synthesizing work.master_clk.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":2221:10:2221:16|Synthesizing work.ehxpllj.syn_black_box.
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Post processing for work.ehxpllj.syn_black_box
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Post processing for work.master_clk.structure
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Post processing for work.fleafpga_uno_e1.arch
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@N: CL201 :"C:\Dev\Apple1Display\UART_RX.vhd":62:4:62:5|Trying to extract state machine for register r_SM_Main.
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Extracted state machine for register r_SM_Main
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State machine has 5 reachable states with original encodings of:
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00001
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00010
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00100
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01000
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10000
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@W: CL249 :"C:\Dev\Apple1Display\UART_RX.vhd":62:4:62:5|Initial value is not supported on state machine r_SM_Main
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@N: CL189 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":165:2:165:3|Register bit flash_count(23) is always 1.
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@W: CL260 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":165:2:165:3|Pruning register bit 23 of flash_count(23 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:10 2019
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###########################################################]
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Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
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@N|Running in 64-bit mode
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File C:\Dev\Apple1Display\impl1\synwork\layer0.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:10 2019
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Aug 8 18:39:10 2019
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###########################################################]
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