95 lines
8.0 KiB
Plaintext
95 lines
8.0 KiB
Plaintext
# Thu Aug 8 18:39:11 2019
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Dev\Apple1Display\impl1\Apple1Display_impl1_scck.rpt
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Printing clock summary report in "C:\Dev\Apple1Display\impl1\Apple1Display_impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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@W: BN287 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Register states[3:0] with reset has an initial value of 1. Ignoring initial value.
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@W: BN287 :"c:\dev\apple1display\ttl\dm74174.vhd":34:2:34:3|Register states[5:0] with reset has an initial value of 1. Ignoring initial value.
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@N: BN362 :"c:\dev\apple1display\uart_rx.vhd":62:4:62:5|Removing sequential instance r_RX_Byte[7] (in view: work.UART_RX(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=26 set on top level netlist FleaFPGA_Uno_E1
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------------------------------------------------------------------------
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0 - System 1.0 MHz 1000.000 system system_clkgroup 0
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0 - dm7427|y1_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_3 83
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0 - FleaFPGA_Uno_E1|sys_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 57
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0 - dm7400_1|y3_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_2 44
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0 - dm74175|q0_i_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_5 13
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1 . dm74161_4|count_derived_clock[3] 1.0 MHz 1000.000 derived (from dm74175|q0_i_inferred_clock) Inferred_clkgroup_5 21
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0 - dm7400_1|y1_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_4 7
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0 - master_clk|CLKOS_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 6
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=========================================================================================================================================================
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@W: MT529 :"c:\dev\apple1display\uart_rx.vhd":37:36:37:38|Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\dev\apple1display\sig2504.vhd":187:4:187:15|Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.D5a.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\dev\apple1display\shiftreg40.vhd":186:4:186:15|Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
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original code -> new code
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00001 -> 000
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00010 -> 001
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00100 -> 010
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01000 -> 011
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10000 -> 100
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Thu Aug 8 18:39:12 2019
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###########################################################]
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