Apple-1-HW
/
Apple1Display
mirror of https://github.com/Myndale/Apple1Display.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Apple1Display/impl1/timing.tpf_hold.html

787 lines
64 KiB
HTML
Raw Permalink Blame History

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<STYLE type=text/css>
<!--
.blink {text-decoration:blink}
.ms {font-size: 9pt; font-family: monospace; font-weight: normal}
.msb {font-size: 9pt; font-family: monospace; font-weight: bold }
-->
</STYLE>
<META content="MSHTML 6.00.2900.2180" name=GENERATOR></HEAD>
<BODY><B>
</B>
<BR><PRE><A name="Report Header"></A>
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.2.115
Mon Aug 05 08:54:32 2019
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: FleaFPGA_Uno_E1
Device,speed: LCMXO2-7000HC,M
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
</A><A name="FREQUENCY PORT 'sys_clock' 25.000000 MH"></A>================================================================================
Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
10 items scored, 6 timing errors detected.
--------------------------------------------------------------------------------
<font color=#FF0000>
Error: The following path exceeds requirements by 0.719ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/SLICE_45">apple_module/rd[7]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.808ns (29.0% logic, 71.0% route), 2 logic levels.
Constraint Details:
0.808ns physical path delay apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
0.051ns DATA_HLD and
0.000ns delay constraint less
-1.476ns skew less
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.719ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15B.CLK,R15C15B.Q1,apple_module/SLICE_45:ROUTE, 0.254,R15C15B.Q1,R14C14D.D0,apple_module/rd[7]:CTOF_DEL, 0.101,R14C14D.D0,R14C14D.F0,apple_module/SLICE_53:ROUTE, 0.320,R14C14D.F0,EBR_R13C10.DIA5,apple_module/un1_a_1[0]">Data path</A> apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C15B.CLK to R15C15B.Q1 <A href="#@comp:apple_module/SLICE_45">apple_module/SLICE_45</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
ROUTE 1 0.254<A href="#@net:apple_module/rd[7]:R15C15B.Q1:R14C14D.D0:0.254"> R15C15B.Q1 to R14C14D.D0 </A> <A href="#@net:apple_module/rd[7]">apple_module/rd[7]</A>
CTOF_DEL --- 0.101 R14C14D.D0 to R14C14D.F0 <A href="#@comp:apple_module/SLICE_53">apple_module/SLICE_53</A>
ROUTE 2 0.320<A href="#@net:apple_module/un1_a_1[0]:R14C14D.F0:EBR_R13C10.DIA5:0.320"> R14C14D.F0 to EBR_R13C10.DIA5</A> <A href="#@net:apple_module/un1_a_1[0]">apple_module/un1_a_1[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.808 (29.0% logic, 71.0% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15B.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_45:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15B.CLK:1.031"> R14C18C.F1 to R15C15B.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
--------
3.051 (25.6% logic, 74.4% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
4.527 (21.1% logic, 78.9% route), 5 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<font color=#FF0000>
Error: The following path exceeds requirements by 0.689ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/SLICE_45">apple_module/rd[5]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.838ns (27.9% logic, 72.1% route), 2 logic levels.
Constraint Details:
0.838ns physical path delay apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
0.051ns DATA_HLD and
0.000ns delay constraint less
-1.476ns skew less
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.689ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15B.CLK,R15C15B.Q0,apple_module/SLICE_45:ROUTE, 0.171,R15C15B.Q0,R14C15A.D0,apple_module/rd[5]:CTOF_DEL, 0.101,R14C15A.D0,R14C15A.F0,apple_module/SLICE_54:ROUTE, 0.433,R14C15A.F0,EBR_R13C10.DIA4,apple_module/un1_a_3[0]">Data path</A> apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C15B.CLK to R15C15B.Q0 <A href="#@comp:apple_module/SLICE_45">apple_module/SLICE_45</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
ROUTE 1 0.171<A href="#@net:apple_module/rd[5]:R15C15B.Q0:R14C15A.D0:0.171"> R15C15B.Q0 to R14C15A.D0 </A> <A href="#@net:apple_module/rd[5]">apple_module/rd[5]</A>
CTOF_DEL --- 0.101 R14C15A.D0 to R14C15A.F0 <A href="#@comp:apple_module/SLICE_54">apple_module/SLICE_54</A>
ROUTE 2 0.433<A href="#@net:apple_module/un1_a_3[0]:R14C15A.F0:EBR_R13C10.DIA4:0.433"> R14C15A.F0 to EBR_R13C10.DIA4</A> <A href="#@net:apple_module/un1_a_3[0]">apple_module/un1_a_3[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.838 (27.9% logic, 72.1% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15B.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_45:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15B.CLK:1.031"> R14C18C.F1 to R15C15B.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
--------
3.051 (25.6% logic, 74.4% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
4.527 (21.1% logic, 78.9% route), 5 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<font color=#FF0000>
Error: The following path exceeds requirements by 0.649ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/SLICE_43">apple_module/rd[1]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.878ns (26.7% logic, 73.3% route), 2 logic levels.
Constraint Details:
0.878ns physical path delay apple_module/SLICE_43 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
0.051ns DATA_HLD and
0.000ns delay constraint less
-1.476ns skew less
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.649ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15A.CLK,R15C15A.Q0,apple_module/SLICE_43:ROUTE, 0.211,R15C15A.Q0,R14C15C.A0,apple_module/rd[1]:CTOF_DEL, 0.101,R14C15C.A0,R14C15C.F0,apple_module/SLICE_58:ROUTE, 0.433,R14C15C.F0,EBR_R13C10.DIA0,apple_module/buffer_char_in[0]">Data path</A> apple_module/SLICE_43 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C15A.CLK to R15C15A.Q0 <A href="#@comp:apple_module/SLICE_43">apple_module/SLICE_43</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
ROUTE 1 0.211<A href="#@net:apple_module/rd[1]:R15C15A.Q0:R14C15C.A0:0.211"> R15C15A.Q0 to R14C15C.A0 </A> <A href="#@net:apple_module/rd[1]">apple_module/rd[1]</A>
CTOF_DEL --- 0.101 R14C15C.A0 to R14C15C.F0 <A href="#@comp:apple_module/SLICE_58">apple_module/SLICE_58</A>
ROUTE 2 0.433<A href="#@net:apple_module/buffer_char_in[0]:R14C15C.F0:EBR_R13C10.DIA0:0.433"> R14C15C.F0 to EBR_R13C10.DIA0</A> <A href="#@net:apple_module/buffer_char_in[0]">apple_module/buffer_char_in[0]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.878 (26.7% logic, 73.3% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15A.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_43:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15A.CLK:1.031"> R14C18C.F1 to R15C15A.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
--------
3.051 (25.6% logic, 74.4% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
4.527 (21.1% logic, 78.9% route), 5 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<font color=#FF0000>
Error: The following path exceeds requirements by 0.633ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/SLICE_43">apple_module/rd[2]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.894ns (26.2% logic, 73.8% route), 2 logic levels.
Constraint Details:
0.894ns physical path delay apple_module/SLICE_43 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
0.051ns DATA_HLD and
0.000ns delay constraint less
-1.476ns skew less
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.633ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15A.CLK,R15C15A.Q1,apple_module/SLICE_43:ROUTE, 0.307,R15C15A.Q1,R14C14A.B0,apple_module/rd[2]:CTOF_DEL, 0.101,R14C14A.B0,R14C14A.F0,apple_module/SLICE_57:ROUTE, 0.353,R14C14A.F0,EBR_R13C10.DIA1,apple_module/buffer_char_in[1]">Data path</A> apple_module/SLICE_43 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C15A.CLK to R15C15A.Q1 <A href="#@comp:apple_module/SLICE_43">apple_module/SLICE_43</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
ROUTE 1 0.307<A href="#@net:apple_module/rd[2]:R15C15A.Q1:R14C14A.B0:0.307"> R15C15A.Q1 to R14C14A.B0 </A> <A href="#@net:apple_module/rd[2]">apple_module/rd[2]</A>
CTOF_DEL --- 0.101 R14C14A.B0 to R14C14A.F0 <A href="#@comp:apple_module/SLICE_57">apple_module/SLICE_57</A>
ROUTE 2 0.353<A href="#@net:apple_module/buffer_char_in[1]:R14C14A.F0:EBR_R13C10.DIA1:0.353"> R14C14A.F0 to EBR_R13C10.DIA1</A> <A href="#@net:apple_module/buffer_char_in[1]">apple_module/buffer_char_in[1]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.894 (26.2% logic, 73.8% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15A.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_43:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15A.CLK:1.031"> R14C18C.F1 to R15C15A.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
--------
3.051 (25.6% logic, 74.4% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
4.527 (21.1% logic, 78.9% route), 5 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<font color=#FF0000>
Error: The following path exceeds requirements by 0.589ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/SLICE_44">apple_module/rd[3]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.938ns (24.9% logic, 75.1% route), 2 logic levels.
Constraint Details:
0.938ns physical path delay apple_module/SLICE_44 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
0.051ns DATA_HLD and
0.000ns delay constraint less
-1.476ns skew less
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.589ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15D.CLK,R15C15D.Q0,apple_module/SLICE_44:ROUTE, 0.247,R15C15D.Q0,R14C15B.A0,apple_module/rd[3]:CTOF_DEL, 0.101,R14C15B.A0,R14C15B.F0,apple_module/SLICE_56:ROUTE, 0.457,R14C15B.F0,EBR_R13C10.DIA2,apple_module/buffer_char_in[2]">Data path</A> apple_module/SLICE_44 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C15D.CLK to R15C15D.Q0 <A href="#@comp:apple_module/SLICE_44">apple_module/SLICE_44</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
ROUTE 1 0.247<A href="#@net:apple_module/rd[3]:R15C15D.Q0:R14C15B.A0:0.247"> R15C15D.Q0 to R14C15B.A0 </A> <A href="#@net:apple_module/rd[3]">apple_module/rd[3]</A>
CTOF_DEL --- 0.101 R14C15B.A0 to R14C15B.F0 <A href="#@comp:apple_module/SLICE_56">apple_module/SLICE_56</A>
ROUTE 2 0.457<A href="#@net:apple_module/buffer_char_in[2]:R14C15B.F0:EBR_R13C10.DIA2:0.457"> R14C15B.F0 to EBR_R13C10.DIA2</A> <A href="#@net:apple_module/buffer_char_in[2]">apple_module/buffer_char_in[2]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.938 (24.9% logic, 75.1% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15D.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_44:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15D.CLK:1.031"> R14C18C.F1 to R15C15D.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
--------
3.051 (25.6% logic, 74.4% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
4.527 (21.1% logic, 78.9% route), 5 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<font color=#FF0000>
Error: The following path exceeds requirements by 0.581ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/SLICE_44">apple_module/rd[4]</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.946ns (24.7% logic, 75.3% route), 2 logic levels.
Constraint Details:
0.946ns physical path delay apple_module/SLICE_44 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
0.051ns DATA_HLD and
0.000ns delay constraint less
-1.476ns skew less
0.000ns feedback compensation requirement (totaling 1.527ns) by 0.581ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R15C15D.CLK,R15C15D.Q1,apple_module/SLICE_44:ROUTE, 0.359,R15C15D.Q1,R14C15D.A0,apple_module/rd[4]:CTOF_DEL, 0.101,R14C15D.A0,R14C15D.F0,apple_module/SLICE_55:ROUTE, 0.353,R14C15D.F0,EBR_R13C10.DIA3,apple_module/buffer_char_in[3]">Data path</A> apple_module/SLICE_44 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C15D.CLK to R15C15D.Q1 <A href="#@comp:apple_module/SLICE_44">apple_module/SLICE_44</A> (from <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>)
ROUTE 1 0.359<A href="#@net:apple_module/rd[4]:R15C15D.Q1:R14C15D.A0:0.359"> R15C15D.Q1 to R14C15D.A0 </A> <A href="#@net:apple_module/rd[4]">apple_module/rd[4]</A>
CTOF_DEL --- 0.101 R14C15D.A0 to R14C15D.F0 <A href="#@comp:apple_module/SLICE_55">apple_module/SLICE_55</A>
ROUTE 2 0.353<A href="#@net:apple_module/buffer_char_in[3]:R14C15D.F0:EBR_R13C10.DIA3:0.353"> R14C15D.F0 to EBR_R13C10.DIA3</A> <A href="#@net:apple_module/buffer_char_in[3]">apple_module/buffer_char_in[3]</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.946 (24.7% logic, 75.3% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R14C18D.CLK,circuit_clk:REG_DEL, 0.154,R14C18D.CLK,R14C18D.Q1,apple_module/D9/SLICE_34:ROUTE, 0.269,R14C18D.Q1,R14C18C.C1,apple_module/count_0[3]:CTOF_DEL, 0.177,R14C18C.C1,R14C18C.F1,apple_module/D1/SLICE_52:ROUTE, 1.031,R14C18C.F1,R15C15D.CLK,apple_module/y2_1">Source Clock Path</A> sys_clock to apple_module/SLICE_44:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R14C18D.CLK:0.707"> RPLL.CLKOS to R14C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R14C18D.CLK to R14C18D.Q1 <A href="#@comp:apple_module/D9/SLICE_34">apple_module/D9/SLICE_34</A>
ROUTE 3 0.269<A href="#@net:apple_module/count_0[3]:R14C18D.Q1:R14C18C.C1:0.269"> R14C18D.Q1 to R14C18C.C1 </A> <A href="#@net:apple_module/count_0[3]">apple_module/count_0[3]</A>
CTOF_DEL --- 0.177 R14C18C.C1 to R14C18C.F1 <A href="#@comp:apple_module/D1/SLICE_52">apple_module/D1/SLICE_52</A>
ROUTE 16 1.031<A href="#@net:apple_module/y2_1:R14C18C.F1:R15C15D.CLK:1.031"> R14C18C.F1 to R15C15D.CLK </A> <A href="#@net:apple_module/y2_1">apple_module/y2_1</A>
--------
3.051 (25.6% logic, 74.4% route), 4 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:PADI_DEL, 0.449,126.PAD,126.PADDI,sys_clock:ROUTE, 0.264,126.PADDI,RPLL.CLKI,sys_clock_c:CLKI2OS_DEL, 0.000,RPLL.CLKI,RPLL.CLKOS,clock_module/PLLInst_0:ROUTE, 0.707,RPLL.CLKOS,R15C18D.CLK,circuit_clk:REG_DEL, 0.154,R15C18D.CLK,R15C18D.Q1,apple_module/D7/SLICE_41:ROUTE, 0.432,R15C18D.Q1,R14C19C.A1,apple_module/horz_count_upper[2]:CTOF_DEL, 0.177,R14C19C.A1,R14C19C.F1,apple_module/SLICE_26:ROUTE, 0.765,R14C19C.F1,R2C19C.B0,apple_module/line_clock:CTOF_DEL, 0.177,R2C19C.B0,R2C19C.F0,apple_module/SLICE_64:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 126.PAD to 126.PADDI <A href="#@comp:sys_clock">sys_clock</A>
ROUTE 1 0.264<A href="#@net:sys_clock_c:126.PADDI:RPLL.CLKI:0.264"> 126.PADDI to RPLL.CLKI </A> <A href="#@net:sys_clock_c">sys_clock_c</A>
CLKI2OS_DE --- 0.000 RPLL.CLKI to RPLL.CLKOS <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 26 0.707<A href="#@net:circuit_clk:RPLL.CLKOS:R15C18D.CLK:0.707"> RPLL.CLKOS to R15C18D.CLK </A> <A href="#@net:circuit_clk">circuit_clk</A>
REG_DEL --- 0.154 R15C18D.CLK to R15C18D.Q1 <A href="#@comp:apple_module/D7/SLICE_41">apple_module/D7/SLICE_41</A>
ROUTE 7 0.432<A href="#@net:apple_module/horz_count_upper[2]:R15C18D.Q1:R14C19C.A1:0.432"> R15C18D.Q1 to R14C19C.A1 </A> <A href="#@net:apple_module/horz_count_upper[2]">apple_module/horz_count_upper[2]</A>
CTOF_DEL --- 0.177 R14C19C.A1 to R14C19C.F1 <A href="#@comp:apple_module/SLICE_26">apple_module/SLICE_26</A>
ROUTE 5 0.765<A href="#@net:apple_module/line_clock:R14C19C.F1:R2C19C.B0:0.765"> R14C19C.F1 to R2C19C.B0 </A> <A href="#@net:apple_module/line_clock">apple_module/line_clock</A>
CTOF_DEL --- 0.177 R2C19C.B0 to R2C19C.F0 <A href="#@comp:apple_module/SLICE_64">apple_module/SLICE_64</A>
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
4.527 (21.1% logic, 78.9% route), 5 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2IFB_ --- 0.000 RPLL.CLKFB to RPLL.CLKINTFB <A href="#@comp:clock_module/PLLInst_0">clock_module/PLLInst_0</A>
ROUTE 1 0.000<A href="#@net:clock_module/CLKFB_t:RPLL.CLKINTFB:RPLL.CLKFB:0.000"> RPLL.CLKINTFB to RPLL.CLKFB </A> <A href="#@net:clock_module/CLKFB_t">clock_module/CLKFB_t</A>
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.221ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/ScreenBuffer/SLICE_9">apple_module/ScreenBuffer/FF_6</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.327ns (40.7% logic, 59.3% route), 1 logic levels.
Constraint Details:
0.327ns physical path delay apple_module/ScreenBuffer/SLICE_9 to apple_module/ScreenBuffer/sram_1_0_0_0 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.221ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C11C.CLK,R14C11C.Q1,apple_module/ScreenBuffer/SLICE_9:ROUTE, 0.194,R14C11C.Q1,EBR_R13C10.ADA6,apple_module/ScreenBuffer/shreg_addr_w3">Data path</A> apple_module/ScreenBuffer/SLICE_9 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C11C.CLK to R14C11C.Q1 <A href="#@comp:apple_module/ScreenBuffer/SLICE_9">apple_module/ScreenBuffer/SLICE_9</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
ROUTE 3 0.194<A href="#@net:apple_module/ScreenBuffer/shreg_addr_w3:R14C11C.Q1:EBR_R13C10.ADA6:0.194"> R14C11C.Q1 to EBR_R13C10.ADA6</A> <A href="#@net:apple_module/ScreenBuffer/shreg_addr_w3">apple_module/ScreenBuffer/shreg_addr_w3</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.327 (40.7% logic, 59.3% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.348,R2C19C.F0,R14C11C.CLK,apple_module/mem0">Source Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.348<A href="#@net:apple_module/mem0:R2C19C.F0:R14C11C.CLK:1.348"> R2C19C.F0 to R14C11C.CLK </A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.348 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.402 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.221ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/ScreenBuffer/SLICE_10">apple_module/ScreenBuffer/FF_5</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.327ns (40.7% logic, 59.3% route), 1 logic levels.
Constraint Details:
0.327ns physical path delay apple_module/ScreenBuffer/SLICE_10 to apple_module/ScreenBuffer/sram_1_0_0_0 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.221ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C11D.CLK,R14C11D.Q0,apple_module/ScreenBuffer/SLICE_10:ROUTE, 0.194,R14C11D.Q0,EBR_R13C10.ADA7,apple_module/ScreenBuffer/shreg_addr_w4">Data path</A> apple_module/ScreenBuffer/SLICE_10 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C11D.CLK to R14C11D.Q0 <A href="#@comp:apple_module/ScreenBuffer/SLICE_10">apple_module/ScreenBuffer/SLICE_10</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
ROUTE 3 0.194<A href="#@net:apple_module/ScreenBuffer/shreg_addr_w4:R14C11D.Q0:EBR_R13C10.ADA7:0.194"> R14C11D.Q0 to EBR_R13C10.ADA7</A> <A href="#@net:apple_module/ScreenBuffer/shreg_addr_w4">apple_module/ScreenBuffer/shreg_addr_w4</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.327 (40.7% logic, 59.3% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.348,R2C19C.F0,R14C11D.CLK,apple_module/mem0">Source Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.348<A href="#@net:apple_module/mem0:R2C19C.F0:R14C11D.CLK:1.348"> R2C19C.F0 to R14C11D.CLK </A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.348 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.402 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.305ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/ScreenBuffer/SLICE_11">apple_module/ScreenBuffer/FF_3</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.411ns (32.4% logic, 67.6% route), 1 logic levels.
Constraint Details:
0.411ns physical path delay apple_module/ScreenBuffer/SLICE_11 to apple_module/ScreenBuffer/sram_1_0_0_0 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.305ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C12A.CLK,R14C12A.Q0,apple_module/ScreenBuffer/SLICE_11:ROUTE, 0.278,R14C12A.Q0,EBR_R13C10.ADA9,apple_module/ScreenBuffer/shreg_addr_w6">Data path</A> apple_module/ScreenBuffer/SLICE_11 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C12A.CLK to R14C12A.Q0 <A href="#@comp:apple_module/ScreenBuffer/SLICE_11">apple_module/ScreenBuffer/SLICE_11</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
ROUTE 3 0.278<A href="#@net:apple_module/ScreenBuffer/shreg_addr_w6:R14C12A.Q0:EBR_R13C10.ADA9:0.278"> R14C12A.Q0 to EBR_R13C10.ADA9</A> <A href="#@net:apple_module/ScreenBuffer/shreg_addr_w6">apple_module/ScreenBuffer/shreg_addr_w6</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.411 (32.4% logic, 67.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.348,R2C19C.F0,R14C12A.CLK,apple_module/mem0">Source Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.348<A href="#@net:apple_module/mem0:R2C19C.F0:R14C12A.CLK:1.348"> R2C19C.F0 to R14C12A.CLK </A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.348 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.402 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.321ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:apple_module/ScreenBuffer/SLICE_8">apple_module/ScreenBuffer/FF_9</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Destination: DP8KC Port <A href="#@comp:apple_module/ScreenBuffer/sram_1_0_0_0">apple_module/ScreenBuffer/sram_1_0_0_0</A>(ASIC) (to <A href="#@net:apple_module/mem0">apple_module/mem0</A> -)
Delay: 0.427ns (31.1% logic, 68.9% route), 1 logic levels.
Constraint Details:
0.427ns physical path delay apple_module/ScreenBuffer/SLICE_8 to apple_module/ScreenBuffer/sram_1_0_0_0 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.321ns
Physical Path Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:REG_DEL, 0.133,R14C11B.CLK,R14C11B.Q0,apple_module/ScreenBuffer/SLICE_8:ROUTE, 0.294,R14C11B.Q0,EBR_R13C10.ADA3,apple_module/ScreenBuffer/shreg_addr_w0">Data path</A> apple_module/ScreenBuffer/SLICE_8 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C11B.CLK to R14C11B.Q0 <A href="#@comp:apple_module/ScreenBuffer/SLICE_8">apple_module/ScreenBuffer/SLICE_8</A> (from <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
ROUTE 3 0.294<A href="#@net:apple_module/ScreenBuffer/shreg_addr_w0:R14C11B.Q0:EBR_R13C10.ADA3:0.294"> R14C11B.Q0 to EBR_R13C10.ADA3</A> <A href="#@net:apple_module/ScreenBuffer/shreg_addr_w0">apple_module/ScreenBuffer/shreg_addr_w0</A> (to <A href="#@net:apple_module/mem0">apple_module/mem0</A>)
--------
0.427 (31.1% logic, 68.9% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.348,R2C19C.F0,R14C11B.CLK,apple_module/mem0">Source Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.348<A href="#@net:apple_module/mem0:R2C19C.F0:R14C11B.CLK:1.348"> R2C19C.F0 to R14C11B.CLK </A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.348 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:FREQUENCY PORT 'sys_clock' 25.000000 MHz ;:ROUTE, 1.402,R2C19C.F0,EBR_R13C10.CLKA,apple_module/mem0">Destination Clock Path</A> apple_module/SLICE_64 to apple_module/ScreenBuffer/sram_1_0_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.402<A href="#@net:apple_module/mem0:R2C19C.F0:EBR_R13C10.CLKA:1.402"> R2C19C.F0 to EBR_R13C10.CLKA</A> <A href="#@net:apple_module/mem0">apple_module/mem0</A>
--------
1.402 (0.0% logic, 100.0% route), 0 logic levels.
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "sys_clock" 25.000000 | | |
MHz ; | -| -| 2 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
apple_module/buffer_char_in[0] | 2| 1| 16.67%
| | |
apple_module/rd[1] | 1| 1| 16.67%
| | |
apple_module/buffer_char_in[1] | 2| 1| 16.67%
| | |
apple_module/rd[2] | 1| 1| 16.67%
| | |
apple_module/buffer_char_in[2] | 2| 1| 16.67%
| | |
apple_module/rd[3] | 1| 1| 16.67%
| | |
apple_module/buffer_char_in[3] | 2| 1| 16.67%
| | |
apple_module/rd[4] | 1| 1| 16.67%
| | |
apple_module/un1_a_3[0] | 2| 1| 16.67%
| | |
apple_module/un1_a_1[0] | 2| 1| 16.67%
| | |
apple_module/rd[7] | 1| 1| 16.67%
| | |
apple_module/rd[5] | 1| 1| 16.67%
| | |
----------------------------------------------------------------------------
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 7 clocks:
Clock Domain: <A href="#@net:apple_module/un1_rda_1">apple_module/un1_rda_1</A> Source: apple_module/SLICE_68.F1 Loads: 1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
Data transfers from:
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 55
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
Clock Domain: <A href="#@net:circuit_clk">circuit_clk</A> Source: clock_module/PLLInst_0.CLKOS
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1 Loads: 16
No transfer within this clock domain is found
Clock Domain: <A href="#@net:apple_module/y2_1">apple_module/y2_1</A> Source: apple_module/D1/SLICE_52.F1 Loads: 16
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
Data transfers from:
Clock Domain: <A href="#@net:apple_module/un1_rda_1">apple_module/un1_rda_1</A> Source: apple_module/SLICE_68.F1 Loads: 1
No transfer within this clock domain is found
Clock Domain: <A href="#@net:apple_module/un1_rda_1">apple_module/un1_rda_1</A> Source: apple_module/SLICE_68.F1 Loads: 1
No transfer within this clock domain is found
Clock Domain: <A href="#@net:circuit_clk">circuit_clk</A> Source: clock_module/PLLInst_0.CLKOS Loads: 26
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
Data transfers from:
Clock Domain: <A href="#@net:apple_module/line_clock">apple_module/line_clock</A> Source: apple_module/SLICE_26.F1
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 6
Clock Domain: <A href="#@net:apple_module/mem0">apple_module/mem0</A> Source: apple_module/SLICE_64.F0
Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 2
Clock Domain: <A href="#@net:sys_clock_c">sys_clock_c</A> Source: sys_clock.PAD Loads: 1
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 6 Score: 3860
Cumulative negative slack: 3860
Constraints cover 786 paths, 10 nets, and 594 connections (98.84% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 6 (hold)
Score: 0 (setup), 3860 (hold)
Cumulative negative slack: 3860 (0+3860)
Reference in New Issue View Git Blame Copy Permalink