1375 lines
19 KiB
INI
1375 lines
19 KiB
INI
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[$GENERAL$]
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INIT=Z
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prefix=EDF_
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user_names=no
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edif2sdf_mapfile=
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logfile=efd2vhd.log
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[$EXPORT$]
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FMAP=NO
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HMAP=NO
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[$properties$]
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CYMODE=
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INIT=
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FD INIT=integer
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FDC INIT=integer
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FDCE INIT=integer
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FDCE_1 INIT=integer
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FDCP INIT=integer
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FDCPE INIT=integer
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FDCPE_1 INIT=integer
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FDCP_1 INIT=integer
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FDC_1 INIT=integer
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FDD INIT=integer
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FDDC INIT=integer
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FDDCE INIT=integer
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FDDCP INIT=integer
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FDDCPE INIT=integer
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FDDP INIT=integer
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FDDPE INIT=integer
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FDDRCPE INIT=integer
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FDDRRSE INIT=integer
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FDE INIT=integer
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FDE_1 INIT=integer
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FDP INIT=integer
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FDPE INIT=integer
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FDPE_1 INIT=integer
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FDP_1 INIT=integer
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FDR INIT=integer
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FDRE INIT=integer
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FDRE_1 INIT=integer
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FDRS INIT=integer
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FDRSE INIT=integer
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FDRSE_1 INIT=integer
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FDRS_1 INIT=integer
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FDR_1 INIT=integer
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FDS INIT=integer
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FDSE INIT=integer
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FDSE_1 INIT=integer
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FDS_1 INIT=integer
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FD_1 INIT=integer
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FJKC INIT=integer
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FJKCE INIT=integer
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FJKP INIT=integer
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FJKPE INIT=integer
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FJKRSE INIT=integer
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FJKSRE INIT=integer
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FTC INIT=integer
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FTCE INIT=integer
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FTCLE INIT=integer
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FTCLEX INIT=integer
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FTP INIT=integer
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FTPE INIT=integer
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FTPLE INIT=integer
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FTRSE INIT=integer
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FTRSLE INIT=integer
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FTSRE INIT=integer
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FTSRLE INIT=integer
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FTCP INIT=integer
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GTPA1_DUAL RXPRBSERR_LOOPBACK_0=integer
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GTPA1_DUAL RXPRBSERR_LOOPBACK_1=integer
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GTXE1 RXPRBSERR_LOOPBACK=integer
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IDDR INIT_Q1=integer
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IDDR INIT_Q2=integer
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IDDR2 INIT_Q0=integer
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IDDR2 INIT_Q1=integer
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IDDR_2CLK INIT_Q1=integer
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IDDR_2CLK INIT_Q2=integer
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IFD INIT=integer
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IFD_1 INIT=integer
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IFDI INIT=integer
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IFDI_1 INIT=integer
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IFDX INIT=integer
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IFDX_1 INIT=integer
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IFDXI INIT=integer
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IFDXI_1 INIT=integer
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ILD INIT=integer
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ILD_1 INIT=integer
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ILDI INIT=integer
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ILDI_1 INIT=integer
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ILDX INIT=integer
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ILDX_1 INIT=integer
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ILDXI INIT=integer
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ILDXI_1 INIT=integer
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ISERDES INIT_Q1=integer
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ISERDES INIT_Q2=integer
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ISERDES INIT_Q3=integer
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ISERDES INIT_Q4=integer
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ISERDES SRVAL_Q1=integer
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ISERDES SRVAL_Q2=integer
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ISERDES SRVAL_Q3=integer
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ISERDES SRVAL_Q4=integer
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ISERDES_NODELAY INIT_Q1=integer
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ISERDES_NODELAY INIT_Q2=integer
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ISERDES_NODELAY INIT_Q3=integer
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ISERDES_NODELAY INIT_Q4=integer
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ISERDES_NODELAY SRVAL_Q1=integer
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ISERDES_NODELAY SRVAL_Q2=integer
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ISERDES_NODELAY SRVAL_Q3=integer
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ISERDES_NODELAY SRVAL_Q4=integer
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LD INIT=integer
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LDC INIT=integer
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LDCE INIT=integer
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LDCE_1 INIT=integer
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LDCP INIT=integer
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LDCPE INIT=integer
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LDCPE_1 INIT=integer
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LDCP_1 INIT=integer
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LDC_1 INIT=integer
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LDE INIT=integer
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LDE_1 INIT=integer
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LDG INIT=integer
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LDP INIT=integer
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LDPE INIT=integer
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LDPE_1 INIT=integer
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LDP_1 INIT=integer
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LD_1 INIT=integer
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ODDR INIT=integer
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ODDR2 INIT=integer
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OFD INIT=integer
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OFD_1 INIT=integer
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OFDE INIT=integer
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OFDE_1 INIT=integer
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OFDI INIT=integer
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OFDI_1 INIT=integer
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OFDT INIT=integer
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OFDT_1 INIT=integer
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OFDX INIT=integer
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OFDX_1 INIT=integer
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OFDXI INIT=integer
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OFDXI_1 INIT=integer
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OSERDES INIT_OQ=integer
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OSERDES SRVAL_OQ=integer
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OSERDES INIT_TQ=integer
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OSERDES SRVAL_TQ=integer
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OSERDES INIT_OQ=integer
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OSERDES INIT_TQ=integer
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OSERDES SRVAL_OQ=integer
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OSERDES SRVAL_TQ=integer
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lut_function=
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eqn=
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INIT_00=
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INIT_01=
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INIT_02=
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INIT_03=
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INIT_04=
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INIT_05=
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INIT_06=
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INIT_07=
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INIT_08=
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INIT_09=
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INIT_0A=
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INIT_0B=
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INIT_0C=
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INIT_0D=
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INIT_0E=
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INIT_0F=
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INIT_10=
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INIT_11=
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INIT_12=
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INIT_13=
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INIT_14=
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INIT_15=
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INIT_16=
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INIT_17=
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INIT_18=
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INIT_19=
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INIT_1A=
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INIT_1B=
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INIT_1C=
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INIT_1D=
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INIT_1E=
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INIT_1F=
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INIT_20=
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INIT_21=
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INIT_22=
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INIT_23=
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INIT_24=
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INIT_25=
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INIT_26=
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INIT_27=
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INIT_28=
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INIT_29=
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INIT_2A=
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INIT_2B=
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INIT_2C=
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INIT_2D=
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INIT_2E=
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INIT_2F=
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INIT_30=
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INIT_31=
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INIT_32=
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INIT_33=
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INIT_34=
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INIT_35=
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INIT_36=
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INIT_37=
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INIT_38=
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INIT_39=
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INIT_3A=
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INIT_3B=
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INIT_3C=
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INIT_3D=
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INIT_3E=
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INIT_3F=
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INIT_40=
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INIT_41=
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INIT_42=
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INIT_43=
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INIT_44=
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INIT_45=
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INIT_46=
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INIT_47=
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INIT_48=
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INIT_49=
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INIT_4A=
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INIT_4B=
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INIT_4C=
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INIT_4D=
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INIT_4E=
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INIT_4F=
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INIT_50=
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INIT_51=
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INIT_52=
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INIT_53=
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INIT_54=
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INIT_55=
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INIT_56=
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INIT_57=
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INIT_58=
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INIT_59=
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INIT_5A=
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INIT_5B=
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INIT_5C=
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INIT_5D=
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INIT_5E=
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INIT_5F=
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INIT_60=
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INIT_61=
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INIT_62=
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INIT_63=
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INIT_64=
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INIT_65=
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INIT_66=
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INIT_67=
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INIT_68=
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INIT_69=
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INIT_6A=
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INIT_6B=
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INIT_6C=
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INIT_6D=
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INIT_6E=
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INIT_6F=
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INITP_00=
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INITP_01=
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INITP_02=
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INITP_03=
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INITP_04=
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INITP_05=
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INITP_06=
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INITP_07=
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LPM_TYPE=
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LPM_WIDTH=integer
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LPM_DIRECTION=
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P_WIDTH=
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P_OFFSET=
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CLKDV_DIVIDE=real
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DUTY_CYCLE_CORRECTION=bool
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WIDTH=integer
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DIVIDE1_BY=integer
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DIVIDE2_BY=integer
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TimingChecksOn=bool
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Xon=bool
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MsgOn=bool
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SEL_F500K=bool
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SEL_F16K=bool
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SEL_F490=bool
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SEL_F15=bool
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;added for virtex4 library
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CLKFX_DIVIDE=integer
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CLKFX_MULTIPLY=integer
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CLKIN_DIVIDE_BY_2=bool
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CLKIN_PERIOD=real
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CLKOUT_PHASE_SHIFT=
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CLK_FEEDBACK=
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DCM_PERFORMANCE_MODE=
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DESKEW_ADJUST=
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DFS_FREQUENCY_MODE=
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DLL_FREQUENCY_MODE=
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FACTORY_JF=
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STARTUP_WAIT=bool
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PHASE_SHIFT=integer
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MONITOR_MODE=
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SIM_MONITOR_FILE=
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JTAG_CHAIN=integer
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INIT_OUT=integer
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PRESELECT_I0=bool
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PRESELECT_I1=bool
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BUFR_DIVIDE=
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DSS_MODE=
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AREG=integer
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B_INPUT=
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BREG=integer
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CARRYINREG=integer
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CARRYINSELREG=integer
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CREG=integer
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LEGACY_MODE=
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MREG=integer
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OPMODEREG=integer
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PREG=integer
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SUBTRACTREG=integer
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ALMOST_FULL_OFFSET=
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ALMOST_EMPTY_OFFSET=
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DATA_WIDTH=integer
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FIRST_WORD_FALL_THROUGH=bool
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REFCLKSEL=
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SYNCLK1OUTEN=
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SYNCLK2OUTEN=
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CAPACITANCE=
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IOSTANDARD=
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DIFF_TERM=bool
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ICAP_WIDTH=
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DDR_CLK_EDGE=
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INIT_Q1=
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INIT_Q2=
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INIT_Q3=
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INIT_Q4=
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SRTYPE=
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IOBDELAY=
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IOBDELAY_TYPE=
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IOBDELAY_VALUE=integer
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DRIVE=integer
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SLEW=
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INIT_BITSLIPCNT=
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;INIT_CE= ;2 elems bit_vector
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;INIT_RANK1_PARTIAL= ;5 elems bit_vector
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;INIT_RANK2= ;6 elems bit_vector
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;INIT_RANK3= ;6 elems bit_vector
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BITSLIP_ENABLE=bool
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DATA_RATE=
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INTERFACE_TYPE=
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NUM_CE=integer
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SERDES_MODE=
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SRVAL_Q1=
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SRVAL_Q2=
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SRVAL_Q3=
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SRVAL_Q4=
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INIT_LOADCNT=
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SERDES_MODE=
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DATA_RATE_OQ=
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INIT_OQ=
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;INIT_ORANK1= ;6 elems bit_vector
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INIT_ORANK2_PARTIAL=
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DATA_RATE_TQ=
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TRISTATE_WIDTH=integer
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INIT_TQ=
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INIT_TRANK1=
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SRVAL_OQ=
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SRVAL_TQ=
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EN_REL=bool
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RST_DEASSERT_CLK=
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DOA_REG=integer
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DOB_REG=integer
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INIT_A=
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INIT_B=
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INVERT_CLK_DOA_REG=bool
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INVERT_CLK_DOB_REG=bool
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RAM_EXTENSION_A=
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RAM_EXTENSION_B=
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READ_WIDTH_A=integer
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READ_WIDTH_B=integer
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SIM_COLLISION_CHECK=
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SRVAL_A=
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SRVAL_B=
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WRITE_MODE_A=
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WRITE_MODE_B=
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WRITE_WIDTH_A=integer
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WRITE_WIDTH_B=integer
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SRVAL=
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WRITE_MODE=
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DISABLE_COLLISION_CHECK=bool
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ALIGN_COMMA_WORD=integer
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BANDGAPSEL=bool
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CCCB_ARBITRATOR_DISABLE=bool
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CHAN_BOND_LIMIT=integer
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CHAN_BOND_MODE=
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CHAN_BOND_ONE_SHOT=bool
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;CHAN_BOND_SEQ_1_1= ;11 elems bit_vector
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;CHAN_BOND_SEQ_1_2= ;11 elems bit_vector
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;CHAN_BOND_SEQ_1_3= ;11 elems bit_vector
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;CHAN_BOND_SEQ_1_4= ;11 elems bit_vector
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CHAN_BOND_SEQ_1_MASK=
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;CHAN_BOND_SEQ_2_1= ;11 elems bit_vector
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;CHAN_BOND_SEQ_2_2= ;11 elems bit_vector
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;CHAN_BOND_SEQ_2_3= ;11 elems bit_vector
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;CHAN_BOND_SEQ_2_4= ;11 elems bit_vector
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CHAN_BOND_SEQ_2_MASK=
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CHAN_BOND_SEQ_2_USE=bool
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CHAN_BOND_SEQ_LEN=integer
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CLK_CORRECT_USE=bool
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CLK_COR_8B10B_DE=bool
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CLK_COR_MAX_LAT=integer
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CLK_COR_MIN_LAT=integer
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;CLK_COR_SEQ_1_2= ;11 elems bit_vector
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;CLK_COR_SEQ_1_3= ;11 elems bit_vector
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;CLK_COR_SEQ_1_4= ;11 elems bit_vector
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CLK_COR_SEQ_1_MASK=
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;CLK_COR_SEQ_2_1= ;11 elems bit_vector
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;CLK_COR_SEQ_2_2= ;11 elems bit_vector
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;CLK_COR_SEQ_2_3= ;11 elems bit_vector
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;CLK_COR_SEQ_2_4= ;11 elems bit_vector
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CLK_COR_SEQ_2_MASK=
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CLK_COR_SEQ_2_USE=bool
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CLK_COR_SEQ_DROP=bool
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CLK_COR_SEQ_LEN=integer
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COMMA32=bool
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;COMMA_10B_MASK= ;10 elems bit_vector
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;CYCLE_LIMIT_SEL= ;2 elems bit_vector
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;DCDR_FILTER= ;3 elems bit_vector
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DEC_MCOMMA_DETECT=bool
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DEC_PCOMMA_DETECT=bool
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DEC_VALID_COMMA_ONLY=bool
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;DIGRX_FWDCLK= ;2 elems bit_vector
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DIGRX_SYNC_MODE=bool
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ENABLE_DCDR=bool
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;FDET_HYS_CAL= ;3 elems bit_vector
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;FDET_HYS_SEL= ;3 elems bit_vector
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;FDET_LCK_CAL= ;3 elems bit_vector
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;FDET_LCK_SEL= ;3 elems bit_vector
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;LOOPCAL_WAIT= ;2 elems bit_vector
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MCOMMA_32B_VALUE=
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MCOMMA_DETECT=bool
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OPPOSITE_SELECT=bool
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PCOMMA_32B_VALUE=
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PCOMMA_DETECT=bool
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PCS_BIT_SLIP=bool
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PMACLKENABLE=bool
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PMACOREPWRENABLE=bool
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PMA_BIT_SLIP=bool
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POWER_ENABLE=bool
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REPEATER=bool
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;RXAFEEQ= ;9 elems bit_vector
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;RXASYNCDIVIDE= ;2 elems bit_vector
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RXBY_32=bool
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;RXCDRLOS= ;6 elems bit_vector
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RXCLK0_FORCE_PMACLK=bool
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;RXCLKMODE= ;6 elems bit_vector
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RXCPSEL=bool
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RXCRCCLOCKDOUBLE=bool
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RXCRCENABLE=bool
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RXCRCINITVAL=
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RXCRCINVERTGEN=bool
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RXCRCSAMECLOCK=bool
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;RXCYCLE_LIMIT_SEL= ;2 elems bit_vector
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;RXDATA_SEL= ;2 elems bit_vector
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RXDCCOUPLE=bool
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RXDIGRESET=bool
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RXDIGRX=bool
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RXENABLE=bool
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RXEQ=
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RXFDCAL_CLOCK_DIVIDE=
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;RXFDET_HYS_CAL= ;3 elems bit_vector
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;RXFDET_HYS_SEL= ;3 elems bit_vector
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;RXFDET_LCK_CAL= ;3 elems bit_vector
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;RXFDET_LCK_SEL= ;3 elems bit_vector
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RXLB=bool
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;RXLKADJ= ;5 elems bit_vector
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;RXLOOPCAL_WAIT= ;2 elems bit_vector
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RXLOOPFILT=
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RXOUTDIV2SEL_A=
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RXOUTDIV2SEL_B=
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RXPD=bool
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RXPLLNDIVSEL=
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RXPMACLKSEL=
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;RXRCPADJ= ;3 elems bit_vector
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RXRECCLK1_USE_SYNC=bool
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;RXSLOWDOWN_CAL= ;2 elems bit_vector
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RXTADJ=bool
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RXUSRDIVISOR=integer
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;RXVCODAC_INIT= ;10 elems bit_vector
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RXVCO_CTRL_ENABLE=bool
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RX_BUFFER_USE=bool
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;RX_CLOCK_DIVIDER= ;2 elems bit_vector
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RX_LOS_INVALID_INCR=integer
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RX_LOS_THRESHOLD=integer
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SAMPLE_8X=bool
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SH_CNT_MAX=integer
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SH_INVALID_CNT_MAX=integer
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;SLOWDOWN_CAL= ;2 elems bit_vector
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TXABPMACLKSEL=
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;TXASYNCDIVIDE= ;2 elems bit_vector
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TXCLK0_FORCE_PMACLK=bool
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TXCLKMODE=
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TXCPSEL=bool
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TXCRCCLOCKDOUBLE=bool
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TXCRCENABLE=bool
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TXCRCINITVAL=
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TXCRCINVERTGEN=bool
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TXCRCSAMECLOCK=bool
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;TXDATA_SEL= ;2 elems bit_vector
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;TXDAT_PRDRV_DAC= ;3 elems bit_vector
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;TXDAT_TAP_DAC= ;5 elems bit_vector
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TXENABLE=bool
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TXFDCAL_CLOCK_DIVIDE=
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TXHIGHSIGNALEN=bool
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TXLOOPFILT=
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TXOUTCLK1_USE_SYNC=bool
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TXOUTDIV2SEL=
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TXPD=bool
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TXPHASESEL=bool
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TXPLLNDIVSEL=
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;TXPOST_PRDRV_DAC= ;3 elems bit_vector
|
|
;TXPOST_TAP_DAC= ;5 elems bit_vector
|
|
TXPOST_TAP_PD=bool
|
|
;TXPRE_PRDRV_DAC= ;3 elems bit_vector
|
|
;TXPRE_TAP_DAC= ;5 elems bit_vector
|
|
TXPRE_TAP_PD=bool
|
|
TXSLEWRATE=bool
|
|
TXTERMTRIM=
|
|
TX_BUFFER_USE=bool
|
|
;TX_CLOCK_DIVIDER= ;2 elems bit_vector
|
|
;VCODAC_INIT= ;10 elems bit_vector
|
|
VCO_CTRL_ENABLE=bool
|
|
|
|
|
|
;added for virtex5 library
|
|
A_INPUT=
|
|
ACASCREG=integer
|
|
ALUMODEREG=integer
|
|
AUTORESET_PATTERN_DETEC=bool
|
|
AUTORESET_PATTERN_DETECT_OPTINV=
|
|
BANDWIDTH=
|
|
BCASCREG=integer
|
|
CLKFBOUT_MULT=integer
|
|
CLKFBOUT_PHASE=real
|
|
CLKIN1_PERIOD=real
|
|
CLKIN2_PERIOD=real
|
|
CLKOUT0_DIVIDE=integer
|
|
CLKOUT0_DUTY_CYCLE=real
|
|
CLKOUT0_PHASE=real
|
|
CLKOUT1_DIVIDE=integer
|
|
CLKOUT1_DUTY_CYCLE=real
|
|
CLKOUT1_PHASE=real
|
|
CLKOUT2_DIVIDE=integer
|
|
CLKOUT2_DUTY_CYCLE=real
|
|
CLKOUT2_PHASE=real
|
|
CLKOUT3_DIVIDE=integer
|
|
CLKOUT3_DUTY_CYCLE=real
|
|
CLKOUT3_PHASE=real
|
|
CLKOUT4_DIVIDE=integer
|
|
CLKOUT4_DUTY_CYCLE=real
|
|
CLKOUT4_PHASE=real
|
|
CLKOUT5_DIVIDE=integer
|
|
CLKOUT5_DUTY_CYCLE=real
|
|
CLKOUT5_PHASE=real
|
|
COMPENSATION=
|
|
CRC_INIT=
|
|
DELAY_SRC=
|
|
DIVCLK_DIVIDE=integer
|
|
DO_REG=integer
|
|
EN_ECC_READ=bool
|
|
EN_ECC_SCRUB=bool
|
|
EN_ECC_WRITE=bool
|
|
EN_SYN=bool
|
|
IDELAY_TYPE=
|
|
IDELAY_VALUE=integer
|
|
INIT_70=
|
|
INIT_71=
|
|
INIT_72=
|
|
INIT_73=
|
|
INIT_74=
|
|
INIT_75=
|
|
INIT_76=
|
|
INIT_77=
|
|
INIT_78=
|
|
INIT_79=
|
|
INIT_7A=
|
|
INIT_7B=
|
|
INIT_7C=
|
|
INIT_7D=
|
|
INIT_7E=
|
|
INIT_7F=
|
|
INIT_C=
|
|
INIT_D=
|
|
INITP_08=
|
|
INITP_09=
|
|
INITP_0A=
|
|
INITP_0B=
|
|
INITP_0C=
|
|
INITP_0D=
|
|
INITP_0E=
|
|
INITP_0F=
|
|
MASK=
|
|
MULTCARRYINREG=integer
|
|
ODELAY_VALUE=integer
|
|
PATTERN=
|
|
PLL_PMCD_MODE=bool
|
|
POLYNOMIAL=
|
|
REF_JITTER=real
|
|
RESET_ON_LOSS_OF_LOCK=bool
|
|
SEL_MASK=
|
|
SEL_PATTERN=
|
|
SEL_ROUNDING_MASK=
|
|
USE_MULT=
|
|
USE_PATTERN_DETECT=
|
|
USE_SIMD=
|
|
;end of virtex5
|
|
|
|
;added for virtex5 (ise9.1i sp2)
|
|
CLKFBOUT_DESKEW_ADJUST=
|
|
CLKOUT0_DESKEW_ADJUST=
|
|
CLKOUT1_DESKEW_ADJUST=
|
|
CLKOUT2_DESKEW_ADJUST=
|
|
CLKOUT3_DESKEW_ADJUST=
|
|
CLKOUT4_DESKEW_ADJUST=
|
|
CLKOUT5_DESKEW_ADJUST=
|
|
;end of virtex5 (ise9.1i sp2)
|
|
|
|
;added for virtex5 (ise9.2i sp1)
|
|
PCS_COM_CFG=
|
|
SIGNAL_PATTERN=
|
|
INIT_FILE=
|
|
;end of virtex5 (ise9.2i sp1)
|
|
|
|
;added for virtex5 (ise 10.1i)
|
|
SIM_MODE=
|
|
;end
|
|
|
|
;added for spartan6, virtex6 (ise 11.2)
|
|
A0REG=integer
|
|
A1REG=integer
|
|
AC_CAP_DIS_0=bool
|
|
AC_CAP_DIS_1=bool
|
|
ADREG=integer
|
|
AUTORESET_PATDET=
|
|
B0REG=integer
|
|
B1REG=integer
|
|
BUFFER_TYPE=
|
|
BYPASS_GCLK_FF=bool
|
|
CARRYINSEL=
|
|
CARRYOUTREG=integer
|
|
CHAN_BOND_2_MAX_SKEW_0=integer
|
|
CINVCTRL_SEL=bool
|
|
CLK_SEL_TYPE=
|
|
CLKCM_CFG=bool
|
|
CLKFBOUT_MULT_F=real
|
|
CLKFXDV_DIVIDE=integer
|
|
CLKFX_MD_MAX=real
|
|
CLKFBOUT_USE_FINE_PS=bool
|
|
CLKOUT0_DIVIDE_F=real
|
|
CLKOUT0_USE_FINE_PS=bool
|
|
CLKOUT1_USE_FINE_PS=bool
|
|
CLKOUT2_USE_FINE_PS=bool
|
|
CLKOUT3_USE_FINE_PS=bool
|
|
CLKOUT4_CASCADE=bool
|
|
CLKOUT4_USE_FINE_PS=bool
|
|
CLKOUT5_USE_FINE_PS=bool
|
|
CLKOUT6_DIVIDE=integer
|
|
CLKOUT6_DUTY_CYCLE=real
|
|
CLKOUT6_PHASE=real
|
|
CLKOUT6_USE_FINE_PS=bool
|
|
CLKRCV_TRST=bool
|
|
CLOCK_HOLD=bool
|
|
COUNTER_WRAPAROUND=
|
|
DATA_RATE_OT=
|
|
DDR3_DATA=integer
|
|
DISABLE_JTAG=bool
|
|
DIVIDE_BYPASS=bool
|
|
DIVIDE=integer
|
|
DFS_BANDWIDTH=
|
|
DQSMASK_ENABLE=bool
|
|
DYN_CLK_INV_EN=bool
|
|
DYN_CLKDIV_INV_EN=bool
|
|
EN_RSTRAM_A=bool
|
|
EN_RSTRAM_B=bool
|
|
FARSRC=
|
|
HIGH_PERFORMANCE_MODE=bool
|
|
I_INVERT=bool
|
|
IBUF_DELAY_VALUE=
|
|
IBUF_LOW_PWR=bool
|
|
IDELAY2_VALUE=integer
|
|
IDELAY_MODE=
|
|
IFD_DELAY_VALUE=
|
|
ISERDESE1 INIT_Q1=integer
|
|
ISERDESE1 INIT_Q2=integer
|
|
ISERDESE1 INIT_Q3=integer
|
|
ISERDESE1 INIT_Q4=integer
|
|
OSERDESE1 INIT_OQ=integer
|
|
OSERDESE1 INIT_TQ=integer
|
|
INMODEREG=integer
|
|
InstancePath=
|
|
ODELAY_TYPE=
|
|
OFB_USED=bool
|
|
ONESHOT=bool
|
|
OUTPUT_MODE=
|
|
PROG_MD_BANDWIDTH=
|
|
PROG_USR=bool
|
|
RAM_MODE=
|
|
REF_JITTER1=real
|
|
REF_JITTER2=real
|
|
REFCLK_FREQUENCY=real
|
|
;REFCLKOUT_DLY= ;10 elems bit_vector
|
|
RST_PRIORITY_A=
|
|
RST_PRIORITY_B=
|
|
RSTREG_PRIORITY_A=
|
|
RSTREG_PRIORITY_B=
|
|
RSTTYPE=
|
|
SETUP_ALL=
|
|
SIM_DEVICE=
|
|
SIM_EFUSE_VALUE=
|
|
SIM_TAPDELAY_VALUE=integer
|
|
SPREAD_SPECTRUM=
|
|
ISERDESE1 SRVAL_Q1=integer
|
|
ISERDESE1 SRVAL_Q2=integer
|
|
ISERDESE1 SRVAL_Q3=integer
|
|
ISERDESE1 SRVAL_Q4=integer
|
|
OSERDESE1 SRVAL_OQ=integer
|
|
OSERDESE1 SRVAL_TQ=integer
|
|
TRAIN_PATTERN=integer
|
|
USE_DOUBLER=bool
|
|
USE_DPORT=bool
|
|
;end of spartan6, virtex6 (ise 11.2)
|
|
|
|
; added for virtex6 (ise 11.3)
|
|
TX_PMADATA_OPT=integer
|
|
ENABLE_SYNC=bool
|
|
;end of virtex6 (ise 11.3)
|
|
|
|
|
|
; added for virtex7 (ise 13.3)
|
|
IBUFDS_DIFF_OUT_IBUFDISABLE DIFF_TERM=
|
|
IBUFDS_DIFF_OUT_INTERMDISABLE DIFF_TERM=
|
|
IBUFDS_IBUFDISABLE DIFF_TERM=
|
|
IBUFDS_INTERMDISABLE DIFF_TERM=
|
|
IOBUFDS_DCIEN DIFF_TERM=
|
|
IOBUFDS_DIFF_OUT_DCIEN DIFF_TERM=
|
|
IOBUFDS_INTERMDISABLE DIFF_TERM=
|
|
DQS_BIAS_MODE=
|
|
IBUF_IBUFDISABLE IBUF_LOW_PWR=
|
|
IBUF_INTERMDISABLE IBUF_LOW_PWR=
|
|
IBUFDS_DIFF_OUT_IBUFDISABLE IBUF_LOW_PWR=
|
|
IBUFDS_DIFF_OUT_INTERMDISABLE IBUF_LOW_PWR=
|
|
IBUFDS_IBUFDISABLE IBUF_LOW_PWR=
|
|
IBUFDS_INTERMDISABLE IBUF_LOW_PWR=
|
|
IOBUF_DCIEN IBUF_LOW_PWR=
|
|
IOBUF_INTERMDISABLE IBUF_LOW_PWR=
|
|
IOBUFDS_DCIEN IBUF_LOW_PWR=
|
|
IOBUFDS_DIFF_OUT_DCIEN IBUF_LOW_PWR=
|
|
IOBUFDS_INTERMDISABLE IBUF_LOW_PWR=
|
|
MEMREFCLK_PERIOD=real
|
|
PHASEREFCLK_PERIOD=real
|
|
SEL_CLK_OFFSET=integer
|
|
USE_IBUFDISABLE=
|
|
;end of virtex7 (ise 13.3)
|
|
|
|
; added for virtex7 (ise 13.4)
|
|
;CLKSWING_CFG= ;2 elems bit_vector
|
|
SS_EN=
|
|
SS_MODE=
|
|
SS_MOD_PERIOD=integer
|
|
;end of virtex7 (ise 13.4)
|
|
|
|
[$LIBMAP$]
|
|
work=.
|
|
xilinx=xabelsim
|
|
xilinxun=
|
|
simprims=simprim
|
|
DESIGNS=
|
|
|
|
;FPGA Express
|
|
VIRTEXE=VIRTEX
|
|
COOLRUNNER=XC9500
|
|
COOLRUNNER2=COOLRUNNERII
|
|
SPARTAN2E=SPARTAN2E
|
|
SPARTAN3=SPARTAN3
|
|
SPARTAN3A=SPARTAN3A
|
|
SPARTAN3E=SPARTAN3E
|
|
SPARTANXL=SPARTANX
|
|
XC3000A=XC3000
|
|
XC3000L=XC3000
|
|
XC3100A=XC3000
|
|
XC3100L=XC3000
|
|
XC4000EX=XC4000X
|
|
XC4000L=XC4000E
|
|
XC4000XL=XC4000X
|
|
XC4000XLA=XC4000X
|
|
XC4000XV=XC4000X
|
|
XC9500XL=XC9500
|
|
XC9500XV=XC9500
|
|
|
|
;Synplify
|
|
COOLRUNNERII=COOLRUNNERII
|
|
Unilib=unisim
|
|
XC4000=unisim
|
|
XC5000=unisim
|
|
|
|
;Exemplar
|
|
xcv=unisim
|
|
xcv2=unisim
|
|
xcv2p=unisim
|
|
xcve=unisim
|
|
xi3=unisim
|
|
xi31=unisim
|
|
xi31a=unisim
|
|
xi3a=unisim
|
|
xi3l=unisim
|
|
xi3t=unisim
|
|
xi4=unisim
|
|
xi4a=unisim
|
|
xi4e=unisim
|
|
xi4et=unisim
|
|
xi4ex=unisim
|
|
xi4h=unisim
|
|
xi4l=unisim
|
|
xi4t=unisim
|
|
xi4xl=unisim
|
|
xi4xla=unisim
|
|
xi4xv=unisim
|
|
xi5=unisim
|
|
xi5t=unisim
|
|
xi72a=unisim
|
|
xi73=unisim
|
|
xi7t=unisim
|
|
xi95=unisim
|
|
xi95xl=unisim
|
|
xi95xv=unisim
|
|
xis=unisim
|
|
xis2=unisim
|
|
xis2e=unisim
|
|
xis3=unisim
|
|
xisxl=unisim
|
|
Active_lib=
|
|
UnlinkedDesignLibrary=
|
|
|
|
[$GSRGTS$]
|
|
GSR=
|
|
GR=
|
|
GTS=
|
|
PRLD=
|
|
|
|
[$INCLUDE$]
|
|
line1=library IEEE;
|
|
line2=use IEEE.std_logic_1164.all;
|
|
line3=library UNISIM;
|
|
line4=use UNISIM.vcomponents.all;
|
|
line5=library SIMPRIM;
|
|
line6=use SIMPRIM.vcomponents.all;
|
|
|
|
[TBUF]
|
|
.=BUFT
|
|
|
|
[VCC]
|
|
VCC=P
|
|
|
|
[GND]
|
|
ground=G
|
|
|
|
[X_FF]
|
|
IN=I
|
|
OUT=O
|
|
|
|
;[OPAD]
|
|
;OPAD=I
|
|
;PAD=I
|
|
|
|
;[IPAD]
|
|
;IPAD=I
|
|
;PAD=I
|
|
|
|
;[IOPAD]
|
|
;IOPAD=I
|
|
;PAD=I
|
|
|
|
[X_PU]
|
|
OUT=O
|
|
|
|
[X_LATCH]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[X_LATCHE]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[x_tri]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[x_buf]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[x_zero]
|
|
OUT=O
|
|
[x_one]
|
|
OUT=O
|
|
|
|
[x_and2]
|
|
OUT=O
|
|
IN1=I1
|
|
IN0=I0
|
|
|
|
[x_inv]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[x_or2]
|
|
IN0=I0
|
|
IN1=I1
|
|
OUT=O
|
|
|
|
[x_ckbuf]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[x_and3]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
OUT=O
|
|
|
|
[x_and4]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
OUT=O
|
|
|
|
[x_and5]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
OUT=O
|
|
|
|
[x_and6]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
OUT=O
|
|
|
|
[x_and7]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
OUT=O
|
|
|
|
[x_and8]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
OUT=O
|
|
|
|
[x_and16]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
IN8=I8
|
|
IN9=I9
|
|
IN10=I10
|
|
IN11=I11
|
|
IN12=I12
|
|
IN13=I13
|
|
IN14=I14
|
|
IN15=I15
|
|
OUT=O
|
|
|
|
[x_or2]
|
|
IN0=I0
|
|
IN1=I1
|
|
OUT=O
|
|
|
|
[x_or3]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
OUT=O
|
|
|
|
[x_or4]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
OUT=O
|
|
|
|
[x_or5]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
OUT=O
|
|
|
|
[x_or6]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
OUT=O
|
|
|
|
[x_or7]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
OUT=O
|
|
|
|
|
|
[x_or8]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
OUT=O
|
|
|
|
[x_or16]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
IN8=I8
|
|
IN9=I9
|
|
IN10=I10
|
|
IN11=I11
|
|
IN12=I12
|
|
IN13=I13
|
|
IN14=I14
|
|
IN15=I15
|
|
OUT=O
|
|
|
|
[x_xor2]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
OUT=O
|
|
|
|
[x_xor3]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
OUT=O
|
|
|
|
[x_xor4]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
OUT=O
|
|
|
|
[x_xor5]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
OUT=O
|
|
|
|
|
|
[x_lut2]
|
|
OUT=O
|
|
|
|
[x_lut3]
|
|
OUT=O
|
|
|
|
[x_lut4]
|
|
OUT=O
|
|
|
|
[x_RAM16]
|
|
OUT=O
|
|
IN=I
|
|
|
|
[x_RAM32]
|
|
OUT=O
|
|
IN=I
|
|
|
|
[x_RAMS16]
|
|
OUT=O
|
|
IN=I
|
|
|
|
[x_RAMS32]
|
|
OUT=O
|
|
IN=I
|
|
|
|
[x_RAMD16]
|
|
OUT=O
|
|
IN=I
|
|
|
|
[x_RAMD32]
|
|
OUT=O
|
|
IN=I
|
|
|
|
[x_MUX2]
|
|
OUT=O
|
|
INA=IA
|
|
INB=IB
|
|
|
|
[x_OR32]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
IN8=I8
|
|
IN9=I9
|
|
IN10=I10
|
|
IN11=I11
|
|
IN12=I12
|
|
IN13=I13
|
|
IN14=I14
|
|
IN15=I15
|
|
IN16=I16
|
|
IN17=I17
|
|
IN18=I18
|
|
IN19=I19
|
|
IN20=I20
|
|
IN21=I21
|
|
IN22=I22
|
|
IN23=I23
|
|
IN24=I24
|
|
IN25=I25
|
|
IN26=I26
|
|
IN27=I27
|
|
IN28=I28
|
|
IN29=I29
|
|
IN30=I30
|
|
IN31=I31
|
|
OUT=O
|
|
|
|
[x_PD]
|
|
OUT=O
|
|
|
|
[x_XOR16]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
IN8=I8
|
|
IN9=I9
|
|
IN10=I10
|
|
IN11=I11
|
|
IN12=I12
|
|
IN13=I13
|
|
IN14=I14
|
|
IN15=I15
|
|
OUT=O
|
|
|
|
[x_XOR32]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
IN8=I8
|
|
IN9=I9
|
|
IN10=I10
|
|
IN11=I11
|
|
IN12=I12
|
|
IN13=I13
|
|
IN14=I14
|
|
IN15=I15
|
|
IN16=I16
|
|
IN17=I17
|
|
IN18=I18
|
|
IN19=I19
|
|
IN20=I20
|
|
IN21=I21
|
|
IN22=I22
|
|
IN23=I23
|
|
IN24=I24
|
|
IN25=I25
|
|
IN26=I26
|
|
IN27=I27
|
|
IN28=I28
|
|
IN29=I29
|
|
IN30=I30
|
|
IN31=I31
|
|
OUT=O
|
|
|
|
[x_AND32]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
IN8=I8
|
|
IN9=I9
|
|
IN10=I10
|
|
IN11=I11
|
|
IN12=I12
|
|
IN13=I13
|
|
IN14=I14
|
|
IN15=I15
|
|
IN16=I16
|
|
IN17=I17
|
|
IN18=I18
|
|
IN19=I19
|
|
IN20=I20
|
|
IN21=I21
|
|
IN22=I22
|
|
IN23=I23
|
|
IN24=I24
|
|
IN25=I25
|
|
IN26=I26
|
|
IN27=I27
|
|
IN28=I28
|
|
IN29=I29
|
|
IN30=I30
|
|
IN31=I31
|
|
OUT=O
|
|
|
|
[x_XOR6]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
OUT=O
|
|
|
|
[x_XOR7]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
OUT=O
|
|
|
|
[x_XOR8]
|
|
IN0=I0
|
|
IN1=I1
|
|
IN2=I2
|
|
IN3=I3
|
|
IN4=I4
|
|
IN5=I5
|
|
IN6=I6
|
|
IN7=I7
|
|
OUT=O
|
|
|
|
[X_SFF]
|
|
IN=I
|
|
OUT=O
|
|
|
|
[X_SUH]
|
|
IN=I
|
|
|
|
[FDCE]
|
|
GSR=$HIDDEN$
|
|
[FDPE]
|
|
GSR=$HIDDEN$
|
|
[IFDX]
|
|
GSR=$HIDDEN$
|
|
[IFDXI]
|
|
GSR=$HIDDEN$
|
|
[ILDX_1]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[ILDXI_1]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[ILFFX]
|
|
GSR=$HIDDEN$
|
|
[ILFFXI]
|
|
GSR=$HIDDEN$
|
|
[ILFLX_1]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[ILFLXI_1]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[LDCE_1]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[LDPE]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[LDPE_1]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[OAND2]
|
|
GTS=$HIDDEN$
|
|
[OBUF]
|
|
GTS=$HIDDEN$
|
|
[OBUFT]
|
|
GTS=$HIDDEN$
|
|
[OFDTX]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[OFDTXI]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[OFDX]
|
|
GSR=$HIDDEN$
|
|
GTS=$HIDDEN$
|
|
[OFDXI]
|
|
GTS=$HIDDEN$
|
|
GSR=$HIDDEN$
|
|
[OMUX2]
|
|
GTS=$HIDDEN$
|
|
[ONAND2]
|
|
GTS=$HIDDEN$
|
|
[ONOR2]
|
|
GTS=$HIDDEN$
|
|
[OOR2]
|
|
GTS=$HIDDEN$
|
|
[OXNOR2]
|
|
GTS=$HIDDEN$
|
|
[OXOR2]
|
|
GTS=$HIDDEN$
|