35 lines
2.5 KiB
Plaintext
35 lines
2.5 KiB
Plaintext
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="simulation" simType="Active-HDL">
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<Source worklib="work" path="ttl/court161.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm74161.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm74175.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="impl1/Apple1Display.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="impl1/divider.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="impl1/master_clk.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="impl1/source/FleaFPGA_Uno_Top.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7402.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7404.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7408.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7410.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7427.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7432.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7450.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm74157.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm74160.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="tests/divider_tb.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="tests/dm74175_tb.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm7400.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="tests/dm7400_tb.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="tests/dm74161_tb.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="impl1/source/ntsc.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="tests/ntsc_tb.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="tests/Apple1Display_tb.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm74166.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/dm74174.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/2504.vhd" type="VHDL" include="none"/>
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<Source worklib="work" path="ttl/2519.vhd" type="VHDL" include="none"/>
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<SimLib value="pmi_work ovi_machxo2"/>
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<GlbInc value=""/>
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<Macro value=""/>
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<TopModule instance="" language="VHDL" name="FleaFPGA_Uno_E1"/>
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</BaliSimProject>
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