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69 lines
1.4 KiB
VHDL
69 lines
1.4 KiB
VHDL
-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.10.2.115
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.math_real.all;
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use IEEE.numeric_std.all;
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entity tb is
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end entity tb;
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architecture test of tb is
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component ShiftReg40
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port (Din : in std_logic_vector(5 downto 0); Clock: in std_logic;
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ClockEn: in std_logic; Reset: in std_logic;
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Q : out std_logic_vector(5 downto 0)
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);
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end component;
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signal Din : std_logic_vector(5 downto 0) := (others => '0');
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signal Clock: std_logic := '0';
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signal ClockEn: std_logic := '0';
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signal Reset: std_logic := '0';
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signal Q : std_logic_vector(5 downto 0);
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begin
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u1 : ShiftReg40
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port map (Din => Din, Clock => Clock, ClockEn => ClockEn, Reset => Reset,
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Q => Q
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);
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process
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begin
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Din <= (others => '0') ;
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wait for 100 ns;
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wait until Reset = '0';
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for i in 0 to 43 loop
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wait until Clock'event and Clock = '1';
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Din <= Din + '1' after 1 ns;
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end loop;
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wait;
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end process;
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Clock <= not Clock after 5.00 ns;
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process
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begin
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ClockEn <= '0' ;
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wait for 100 ns;
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wait until Reset = '0';
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ClockEn <= '1' ;
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wait;
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end process;
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process
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begin
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Reset <= '1' ;
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wait for 100 ns;
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Reset <= '0' ;
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wait;
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end process;
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end architecture test;
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