32 lines
537 B
VHDL
32 lines
537 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity test_entity is
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port(
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clk: in std_logic;
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clr: in std_logic;
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q: out std_logic_vector(3 downto 0)
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);
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end test_entity;
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architecture behavior OF test_entity is
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signal count: std_logic_vector(3 downto 0) := "0000";
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begin
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process(clk, clr)
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begin
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if (clr='1') then
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count <= "0000";
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elsif rising_edge(clk) then
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count <= count + 1;
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end if;
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end process;
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q <= count;
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end architecture;
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