123 lines
4.8 KiB
VHDL
123 lines
4.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity apple1display_tb is
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end apple1display_tb;
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architecture behavior OF apple1display_tb is
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signal clk: std_logic;
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constant freq: natural := 14_318_180;
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constant period: time := 1 sec / FREQ;
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-- watches
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signal sync : std_logic;
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signal luma : std_logic;
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signal dot_rate : std_logic;
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signal char_rate : std_logic;
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signal col_reset : std_logic;
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signal char_column: std_logic_vector(3 downto 0);
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signal char_address : std_logic_vector(8 downto 0);
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signal horz_count_lower: std_logic_vector(3 downto 0);
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signal horz_count_upper: std_logic_vector(3 downto 0);
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signal vert_count_lower: std_logic_vector(3 downto 0);
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signal vert_count_upper: std_logic_vector(3 downto 0);
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signal sync_count: std_logic_vector(3 downto 0);
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signal h_carry, last_h, load_h: std_logic;
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signal v_carry, last: std_logic;
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signal vbl, vbl_i: std_logic;
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signal hbl_i: std_logic;
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signal vert_in: std_logic;
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signal vinh_start, vinh_l: std_logic;
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signal hsync_i, vsynch_i, sync_i: std_logic;
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signal load_char:std_logic;
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signal load_char_delayed:std_logic;
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signal cur_char:std_logic_vector(4 downto 0);
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signal screen_char:std_logic_vector(5 downto 0);
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signal horz_count :std_logic_vector(7 downto 0);
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signal vert_count :std_logic_vector(7 downto 0);
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signal line_clock:std_logic;
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signal line7:std_logic;
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signal cl:std_logic;
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signal mem0:std_logic;
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signal rd :std_logic_vector(7 downto 0);
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signal da:std_logic := '0';
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signal rda_i:std_logic := '1';
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begin
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dot_rate <= <<signal .apple1display_tb.dut.dot_rate : std_logic>>;
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char_rate <= <<signal .apple1display_tb.dut.char_rate: std_logic>>;
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col_reset <= <<signal .apple1display_tb.dut.col_reset: std_logic>>;
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char_column <= <<signal .apple1display_tb.dut.char_column: std_logic_vector(3 downto 0)>>;
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char_address <= <<signal .apple1display_tb.dut.char_address: std_logic_vector(8 downto 0)>>;
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horz_count_lower <= <<signal .apple1display_tb.dut.horz_count_lower: std_logic_vector(3 downto 0)>>;
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horz_count_upper <= <<signal .apple1display_tb.dut.horz_count_upper: std_logic_vector(3 downto 0)>>;
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horz_count <= <<signal .apple1display_tb.dut.horz_count_upper: std_logic_vector(3 downto 0)>> & <<signal .apple1display_tb.dut.horz_count_lower: std_logic_vector(3 downto 0)>>;
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vert_count_lower <= <<signal .apple1display_tb.dut.vert_count_lower: std_logic_vector(3 downto 0)>>;
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vert_count_upper <= <<signal .apple1display_tb.dut.vert_count_upper: std_logic_vector(3 downto 0)>>;
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vert_count <= <<signal .apple1display_tb.dut.vert_count_upper: std_logic_vector(3 downto 0)>> & <<signal .apple1display_tb.dut.vert_count_lower: std_logic_vector(3 downto 0)>>;
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sync_count <= <<signal .apple1display_tb.dut.sync_count: std_logic_vector(3 downto 0)>>;
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h_carry <= <<signal .apple1display_tb.dut.h_carry: std_logic>>;
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last_h <= <<signal .apple1display_tb.dut.last_h: std_logic>>;
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load_h <= <<signal .apple1display_tb.dut.load_h: std_logic>>;
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v_carry <= <<signal .apple1display_tb.dut.v_carry: std_logic>>;
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last <= <<signal .apple1display_tb.dut.last: std_logic>>;
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vbl <= <<signal .apple1display_tb.dut.vbl: std_logic>>;
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vbl_i <= <<signal .apple1display_tb.dut.vbl_i: std_logic>>;
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hbl_i <= <<signal .apple1display_tb.dut.hbl_i: std_logic>>;
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vert_in <= <<signal .apple1display_tb.dut.vert_in: std_logic>>;
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vinh_start <= <<signal .apple1display_tb.dut.vinh_start: std_logic>>;
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vinh_l <= <<signal .apple1display_tb.dut.vinh_l: std_logic>>;
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hsync_i <= <<signal .apple1display_tb.dut.hsync_i: std_logic>>;
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vsynch_i <= <<signal .apple1display_tb.dut.vsynch_i: std_logic>>;
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sync_i <= <<signal .apple1display_tb.dut.sync_i : std_logic>>;
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load_char <= <<signal .apple1display_tb.dut.load_char:std_logic>>;
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cur_char <= <<signal .apple1display_tb.dut.cur_char:std_logic_vector(4 downto 0)>>;
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screen_char <= <<signal .apple1display_tb.dut.screen_char: std_logic_vector(5 downto 0)>>;
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line_clock <= <<signal .apple1display_tb.dut.line_clock: std_logic>>;
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line7 <= <<signal .apple1display_tb.dut.line7: std_logic>>;
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cl <= <<signal .apple1display_tb.dut.cl: std_logic>>;
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mem0 <= <<signal .apple1display_tb.dut.mem0: std_logic>>;
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dut: entity work.apple1display
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port map(reset => '0', clk => clk, sync => sync, luma => luma, rd => rd(7 downto 1), da => da, rda_i => rda_i);
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process
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-- inject a single master clock pulse
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procedure clock is
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begin
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clk <= '0';
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wait for period/2;
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clk <= '1';
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wait for period/2;
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end procedure clock;
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-- two clocks make a dot pulse
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procedure dot_pulse is
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begin
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clock;
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clock;
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end procedure dot_pulse;
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-- six dot pulses make a char pulse
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procedure char_pulse is
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begin
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dot_pulse;
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dot_pulse;
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dot_pulse;
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dot_pulse;
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dot_pulse;
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dot_pulse;
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end procedure char_pulse;
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begin
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char_pulse;
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char_pulse;
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end process;
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end architecture;
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