39 lines
622 B
VHDL
39 lines
622 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ShiftReg40_tb is
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end ShiftReg40_tb;
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architecture behavior OF ShiftReg40_tb is
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constant freq: natural := 14_318_180;
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constant period: time := 1 sec / FREQ;
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signal clk: std_logic;
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signal q: std_logic_vector(5 downto 0);
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begin
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dut: entity ShiftReg40
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port map (
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Din(5 downto 0)=> q,
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Clock=> clk,
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ClockEn=> '1',
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Reset=> '0',
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Q(5 downto 0)=> q
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);
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process
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begin
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clk <= '0';
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wait for period/2;
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clk <= '1';
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wait for period/2;
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end process;
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end architecture;
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