89 lines
1.5 KiB
VHDL
89 lines
1.5 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity dm74161_tb is
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end dm74161_tb;
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architecture behavior OF dm74161_tb is
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type test_state is (init, counting, load, cet_inhibit, cep_inhibit, finished);
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signal clk, clr_l, load_l, cet, cep: std_logic;
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signal d:std_logic_vector(3 downto 0);
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signal q:std_logic_vector(3 downto 0);
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signal carry: std_logic;
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signal state: test_state;
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begin
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dut: entity work.dm74161
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port map(
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clk => clk, clr_l => clr_l, load_l => load_l, cet => cet, cep => cep,
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d3=>d(3), d2=>d(2), d1=>d(1), d0=>d(0),
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q3=>q(3), q2=>q(2), q1=>q(1), q0=>q(0),
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carry => carry
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);
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process
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begin
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-- init
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state <= init;
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clk <= '0';
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clr_l <= '1';
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load_l <= '1';
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cet <= '1';
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cep <= '1';
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d <= "0000";
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wait for 1ns;
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-- count to 16
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state <= counting;
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for ii in 1 to 3 loop
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clk <= '1';
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wait for 1ns;
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clk <= '0';
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wait for 1ns;
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end loop;
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-- load
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state <= load;
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d <= "1110";
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load_l <= '0';
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clk <= '1';
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wait for 1ns;
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load_l <= '1';
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clk <= '0';
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wait for 1ns;
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-- cet inhibit
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state <= cet_inhibit;
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cet <= '0';
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for ii in 1 to 3 loop
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clk <= '1';
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wait for 1ns;
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clk <= '1';
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wait for 1ns;
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end loop;
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cet <= '1';
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-- cep inhibit
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state <= cep_inhibit;
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cep <= '0';
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for ii in 1 to 3 loop
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clk <= '1';
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wait for 1ns;
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clk <= '0';
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wait for 1ns;
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end loop;
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cep <= '1';
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-- all done
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state <= finished;
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wait;
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end process;
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end architecture;
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