34 lines
527 B
VHDL
34 lines
527 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ntsc_tb is
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end ntsc_tb;
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architecture behavior OF ntsc_tb is
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signal clk: std_logic;
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signal ntsc: std_logic_vector(3 downto 0);
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constant freq: natural := 14_318_180;
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constant period: time := 1 sec / FREQ;
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begin
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dut: entity work.ntsc
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port map(
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clk => clk,
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ntsc => ntsc
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);
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process
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begin
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clk <= '0';
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wait for period;
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clk <= '1';
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wait for period;
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end process;
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end architecture;
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