38 lines
656 B
VHDL
38 lines
656 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- ttl2519 40-bit static shift register
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entity ttl2519 is
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port(
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cl: in std_logic;
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rc: in std_logic;
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i: in std_logic_vector(5 downto 0);
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q: out std_logic_vector(5 downto 0)
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);
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end ttl2519;
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architecture behavior OF ttl2519 is
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signal cur : std_logic_vector(5 downto 0);
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signal input : std_logic_vector(5 downto 0);
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begin
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LineBuffer : entity ShiftReg40
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port map(
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Din => input,
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Clock => cl,
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ClockEn => '1',
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Reset => '0',
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Q => cur
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);
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q <= cur;
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input <= cur when rc = '1'
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else i;
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end architecture;
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