24 lines
351 B
VHDL
24 lines
351 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- DM7400 Quad 2-Input NAND Gate
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entity dm7400 is
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port(
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A1, B1, A2, B2, A3, B3, A4, B4: in std_logic := '0';
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Y1, Y2, Y3, Y4: out std_logic
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);
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end dm7400;
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architecture behavior of dm7400 is
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begin
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Y1 <= A1 nand B1;
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Y2 <= A2 nand B2;
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Y3 <= A3 nand B3;
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Y4 <= A4 nand B4;
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end architecture;
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