27 lines
361 B
VHDL
27 lines
361 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- DM7404 Hex Inverting Gates
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entity dm7404 is
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port(
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A1, A2, A3, A4, A5, A6: in std_logic := '0';
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Y1, Y2, Y3, Y4, Y5, Y6: out std_logic
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);
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end dm7404;
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architecture behavior OF dm7404 IS
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begin
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Y1 <= not A1;
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Y2 <= not A2;
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Y3 <= not A3;
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Y4 <= not A4;
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Y5 <= not A5;
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Y6 <= not A6;
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end architecture;
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