25 lines
373 B
VHDL
25 lines
373 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- DM7410 Triple 3-Input NAND Gates
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entity dm7410 is
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port(
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A1, A2, A3,
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B1, B2, B3,
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C1, C2, C3: in std_logic := '0';
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Y1, Y2, Y3: out std_logic
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);
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end dm7410;
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architecture behavior OF dm7410 IS
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begin
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Y1 <= not (A1 and B1 and C1);
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Y2 <= not (A2 and B2 and C2);
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Y3 <= not (A3 and B3 and C3);
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end architecture;
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