28 lines
612 B
VHDL
28 lines
612 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- DM7432 Quad 2-Input OR Gates
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entity dm74157 is
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port(
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enable: in std_logic;
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sel: in std_logic;
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A: in std_logic_vector(3 downto 0);
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B: in std_logic_vector(3 downto 0);
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Y: out std_logic_vector(3 downto 0)
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);
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end dm74157;
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architecture behavior OF dm74157 IS
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begin
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Y(0) <= ((A(0) and not(sel)) or (B(0) and sel)) and not(enable);
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Y(1) <= ((A(1) and not(sel)) or (B(1) and sel)) and not(enable);
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Y(2) <= ((A(2) and not(sel)) or (B(2) and sel)) and not(enable);
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Y(3) <= ((A(3) and not(sel)) or (B(3) and sel)) and not(enable);
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end architecture;
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