46 lines
1.1 KiB
VHDL
46 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity dm74160 is
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port(
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clk: in std_logic; clr_l: in std_logic; load_l: in std_logic; cet: in std_logic; cep: in std_logic;
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d3, d2, d1, d0: in std_logic;
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q3, q2, q1, q0: out std_logic;
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carry: out std_logic
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);
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end dm74160;
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architecture behavior OF dm74160 is
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constant ZERO : std_logic_vector(3 downto 0) := "0000";
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constant MAX_COUNT: std_logic_vector(3 downto 0) := "1001";
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signal count: std_logic_vector(3 downto 0) := "0000";
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begin
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process(clk, clr_l, load_l, cep, cet)
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begin
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if (clr_l = '0') then
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count <= ZERO; -- reset
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elsif rising_edge(clk) then -- clk rising edge
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if (load_l = '0') then
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count <= d3 & d2 & d1 & d0; -- load
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elsif (cep = '1') and (cet='1') then
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if (count = MAX_COUNT) then
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count <= ZERO; -- overflow
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else
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count <= count + 1; -- inc
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end if;
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end if;
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end if;
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end process;
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(q3, q2, q1, q0) <= std_logic_vector'(ZERO) when clr_l = '0'
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else count;
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carry <= cet when (count = MAX_COUNT) and (clr_l = '1')
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else '0';
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end architecture;
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