45 lines
1001 B
VHDL
45 lines
1001 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity dm74166 is
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port(
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clk1, clk2: in std_logic;
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input, ld, clr_l: in std_logic;
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a, b, c, d, e, f, g, h: in std_logic;
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output: out std_logic
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);
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end dm74166;
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architecture behavior OF dm74166 is
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signal Qa: std_logic := '0';
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signal Qb: std_logic := '0';
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signal Qc: std_logic := '0';
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signal Qd: std_logic := '0';
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signal Qe: std_logic := '0';
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signal Qf: std_logic := '0';
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signal Qg: std_logic := '0';
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signal Qh: std_logic := '0';
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begin
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process(clk1, clk2, clr_l)
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begin
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if (clr_l = '0') then
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Qa<='0'; Qb<='0'; Qc<='0'; Qd<='0'; Qe<='0'; Qf<='0'; Qg<='0'; Qh<='0';
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elsif rising_edge(clk1) or rising_edge(clk2) then
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if ld='0' then
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Qa<=a; Qb<=b; Qc<=c; Qd<=d; Qe<=e; Qf<=f; Qg<=g; Qh<=h;
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else
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Qa<=input; Qb<=Qa; Qc<=Qb; Qd<=Qc; Qe<=Qd; Qf<=Qe; Qg<=Qf; Qh<=Qg;
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end if;
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end if;
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end process;
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output <= Qh when clr_l = '1'
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else '0';
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end architecture;
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