45 lines
900 B
VHDL
45 lines
900 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- dm74174 Hex D-type flip-flop
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entity dm74174 is
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generic(
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s5: std_logic:='0';
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s4: std_logic:='0';
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s3: std_logic:='0';
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s2: std_logic:='0';
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s1: std_logic:='0';
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s0: std_logic:='0'
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);
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port(
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cp: in std_logic;
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mr: in std_logic;
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d5, d4, d3, d2, d1, d0: in std_logic;
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q5, q4, q3, q2, q1, q0: out std_logic;
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q5_i, q4_i, q3_i, q2_i, q1_i, q0_i: out std_logic
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);
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end dm74174;
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architecture behavior OF dm74174 is
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signal states : std_logic_vector(5 downto 0) := s5 & s4 & s3 & s2 & s1 & s0;
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begin
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process(cp, mr)
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begin
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if (mr = '0') then
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states <= "000000";
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elsif rising_edge(cp) then
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states <= d5 & d4 & d3 & d2 & d1 & d0;
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end if;
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end process;
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(q5, q4, q3, q2, q1, q0) <= states;
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(q5_i, q4_i, q3_i, q2_i, q1_i, q0_i) <= not states;
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end architecture;
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