27 lines
458 B
VHDL
27 lines
458 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- DM7450 Dual 2-wide 2-input and-or-invert gates
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entity dm7450 is
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port(
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A1, B1, C1, D1,
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A2, B2, C2, D2: in std_logic := '0';
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X1: in std_logic := '1';
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X1_l: in std_logic := '0';
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Y1, Y2: out std_logic
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);
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end dm7450;
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architecture behavior OF dm7450 IS
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begin
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Y1 <= 'Z' when (X1 = '0') or (X1_l = '1') else
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(A1 and B1) nor (C1 and D1);
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Y2 <= (A2 and B2) nor (C2 and D2);
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end architecture;
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