37 lines
727 B
VHDL
37 lines
727 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.std_logic_arith.all;
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entity ne555 is
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port(
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clk_in: in std_logic;
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clk_out: out std_logic
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);
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end ne555;
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architecture behavior of ne555 is
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signal flash_counter : std_logic_vector(5 downto 0) := "000000";
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constant start_val: std_logic_vector(5 downto 0) := "101101"; -- -19
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constant end_val: std_logic_vector(5 downto 0) := "001011"; -- +11
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begin
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process (clk_in)
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begin
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if rising_edge(clk_in) then
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if flash_counter = end_val then
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flash_counter <= start_val;
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else
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flash_counter <= flash_counter + 1;
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end if;
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end if;
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end process;
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clk_out <= flash_counter(5);
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end architecture;
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